[PATCH] D55722: [DAGCombiner] scalarize binop followed by extractelement

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: andreadb, efriedma, uweigand, RKSimon.
Herald added subscribers: kristof.beyls, javed.absar, mcrosier.

As noted in PR39973 and D55558 <https://reviews.llvm.org/D55558>:
https://bugs.llvm.org/show_bug.cgi?id=39973
...this is a partial implementation of a fold that we do as an IR canonicalization in instcombine:

  // extelt (binop X, Y), Index --> binop (extelt X, Index), (extelt Y, Index)

We want to have this in the DAG too because as we can see in some of the test diffs (reductions), the pattern may not be visible in IR.
Given that this is already an IR canonicalization, any backend that would prefer a vector op over a scalar op is expected to already have the reverse transform in DAG lowering (not sure if that's a realistic expectation though).

There's an ARM test diff that shows that we also have a reverse transform in IR in CGP. I'm not sure what to make of that. Isn't the updated asm better than the existing code for that test?

Note that I changed some existing regression tests leading up to this patch trying to preserve their intent. Let me know if we need to do any more of that for the remaining diffs here. These were the preliminary commits (and so those tests are not affected by this patch):
rL349160 <https://reviews.llvm.org/rL349160>
rL349163 <https://reviews.llvm.org/rL349163>
rL349164 <https://reviews.llvm.org/rL349164>
rL349166 <https://reviews.llvm.org/rL349166>
rL349176 <https://reviews.llvm.org/rL349176>
rL349177 <https://reviews.llvm.org/rL349177>


https://reviews.llvm.org/D55722

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/ARM/vector-promotion.ll
  test/CodeGen/SystemZ/knownbits.ll
  test/CodeGen/SystemZ/vec-trunc-to-i1.ll
  test/CodeGen/X86/and-load-fold.ll
  test/CodeGen/X86/extract-fp.ll
  test/CodeGen/X86/horizontal-reduce-smax.ll
  test/CodeGen/X86/horizontal-reduce-smin.ll
  test/CodeGen/X86/horizontal-reduce-umax.ll
  test/CodeGen/X86/horizontal-reduce-umin.ll
  test/CodeGen/X86/known-bits-vector.ll
  test/CodeGen/X86/known-signbits-vector.ll
  test/CodeGen/X86/pr30511.ll
  test/CodeGen/X86/setcc-combine.ll
  test/CodeGen/X86/shrink_vmul-widen.ll
  test/CodeGen/X86/shrink_vmul.ll
  test/CodeGen/X86/vector-gep.ll
  test/CodeGen/X86/vector-reduce-smax-widen.ll
  test/CodeGen/X86/vector-reduce-smax.ll
  test/CodeGen/X86/vector-reduce-smin-widen.ll
  test/CodeGen/X86/vector-reduce-smin.ll
  test/CodeGen/X86/vector-reduce-umax-widen.ll
  test/CodeGen/X86/vector-reduce-umax.ll
  test/CodeGen/X86/vector-reduce-umin-widen.ll
  test/CodeGen/X86/vector-reduce-umin.ll
  test/CodeGen/X86/vector-rotate-128.ll
  test/CodeGen/X86/xor.ll

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