[llvm] r349186 - [SDAG] Ignore chain operand in REG_SEQUENCE when emitting instructions

[Krzysztof Parzyszek via llvm-commits]

I don't know exactly where this happens.  I can check that next week.

-Krzysztof

On 12/14/2018 4:11 PM, Friedman, Eli wrote:
> On 12/14/2018 12:14 PM, Krzysztof Parzyszek via llvm-commits wrote:
>> Author: kparzysz
>> Date: Fri Dec 14 12:14:12 2018
>> New Revision: 349186
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=349186&view=rev
>> Log:
>> [SDAG] Ignore chain operand in REG_SEQUENCE when emitting instructions
>>
>> Modified:
>>      llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
>> URL: 
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=349186&r1=349185&r2=349186&view=diff 
>>
>> ============================================================================== 
>>
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Fri Dec 14 
>> 12:14:12 2018
>> @@ -652,6 +652,10 @@ void InstrEmitter::EmitRegSequence(SDNod
>>     const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
>>     MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, 
>> NewVReg);
>>     unsigned NumOps = Node->getNumOperands();
>> +  // REG_SEQUENCE can "inherit" a chain from a subnode.
> 
> This seems weird... where is the chain added to the REG_SEQUENCE?  If 
> TableGen pattern matching is somehow adding a chain to a REG_SEQUENCE, 
> we should fix TableGen, I think; even if this workaround works here, it 
> seems like the sort of issue someone will stumble over again with a 
> different instruction.
> 
> -Eli
> 


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