[llvm] r349186 - [SDAG] Ignore chain operand in REG_SEQUENCE when emitting instructions

[Roman Lebedev via llvm-commits]

No test?

On Fri, Dec 14, 2018 at 11:17 PM Krzysztof Parzyszek via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
>
> Author: kparzysz
> Date: Fri Dec 14 12:14:12 2018
> New Revision: 349186
>
> URL: http://llvm.org/viewvc/llvm-project?rev=349186&view=rev
> Log:
> [SDAG] Ignore chain operand in REG_SEQUENCE when emitting instructions
>
> Modified:
>     llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=349186&r1=349185&r2=349186&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Fri Dec 14 12:14:12 2018
> @@ -652,6 +652,10 @@ void InstrEmitter::EmitRegSequence(SDNod
>    const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
>    MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);
>    unsigned NumOps = Node->getNumOperands();
> +  // REG_SEQUENCE can "inherit" a chain from a subnode.
> +  if (NumOps && Node->getOperand(NumOps-1).getValueType() == MVT::Other)
> +    --NumOps; // Ignore chain if it exists.
> +
>    assert((NumOps & 1) == 1 &&
>           "REG_SEQUENCE must have an odd number of operands!");
>    for (unsigned i = 1; i != NumOps; ++i) {
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits