[llvm] r349185 - [AArch64] Simplify the scheduling predicates (NFC)

[Evandro Menezes via llvm-commits]

Author: evandro
Date: Fri Dec 14 12:04:58 2018
New Revision: 349185

URL: http://llvm.org/viewvc/llvm-project?rev=349185&view=rev
Log:
[AArch64] Simplify the scheduling predicates (NFC)

The instruction encodings make it unnecessary to distinguish extended W-form
from X-form instructions.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64SchedPredExynos.td
    llvm/trunk/lib/Target/AArch64/AArch64SchedPredicates.td

Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedPredExynos.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedPredExynos.td?rev=349185&r1=349184&r2=349185&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedPredExynos.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedPredExynos.td Fri Dec 14 12:04:58 2018
@@ -35,21 +35,13 @@ def ExynosExtFn   : TIIPredicate<
                       "isExynosExtFast",
                       MCOpcodeSwitchStatement<
                         [MCOpcodeSwitchCase<
-                           IsArithExt32Op.ValidOpcodes,
+                           IsArithExtOp.ValidOpcodes,
                            MCReturnStatement<
                              CheckAny<[CheckExtBy0,
                                        CheckAll<
-                                         [CheckExtUXTW,
-                                          CheckAny<
-                                            [CheckExtBy1,
-                                             CheckExtBy2,
-                                             CheckExtBy3]>]>]>>>,
-                         MCOpcodeSwitchCase<
-                           IsArithExt64Op.ValidOpcodes,
-                           MCReturnStatement<
-                             CheckAny<[CheckExtBy0,
-                                       CheckAll<
-                                         [CheckExtUXTX,
+                                         [CheckAny<
+                                           [CheckExtUXTW,
+                                            CheckExtUXTX]>,
                                           CheckAny<
                                             [CheckExtBy1,
                                              CheckExtBy2,
@@ -57,6 +49,20 @@ def ExynosExtFn   : TIIPredicate<
                         MCReturnStatement<FalsePred>>>;
 def ExynosExtPred : MCSchedPredicate<ExynosExtFn>;
 
+// Identify a load or store using the register offset addressing mode
+// with a scaled non-extended register.
+def ExynosScaledIdxFn   : TIIPredicate<"isExynosScaledAddr",
+                                       MCOpcodeSwitchStatement<
+                                         [MCOpcodeSwitchCase<
+                                            IsLoadStoreRegOffsetOp.ValidOpcodes,
+                                            MCReturnStatement<
+                                              CheckAny<
+                                                [CheckMemExtSXTW,
+                                                 CheckMemExtUXTW,
+                                                 CheckMemScaled]>>>],
+                                         MCReturnStatement<FalsePred>>>;
+def ExynosScaledIdxPred : MCSchedPredicate<ExynosScaledIdxFn>;
+
 // Identify FP instructions.
 def ExynosFPPred : MCSchedPredicate<CheckAny<[CheckDForm, CheckQForm]>>;
 

Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedPredicates.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedPredicates.td?rev=349185&r1=349184&r2=349185&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedPredicates.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedPredicates.td Fri Dec 14 12:04:58 2018
@@ -132,12 +132,10 @@ def CheckQForm             : CheckAll<[C
                                                  CheckRegOperand<0, Q31>]>]>;
 
 // Identify arithmetic instructions with extend.
-def IsArithExt32Op         : CheckOpcode<[ADDWrx, ADDXrx, ADDSWrx, ADDSXrx,
-                                          SUBWrx, SUBXrx, SUBSWrx, SUBSXrx]>;
-def IsArithExt64Op         : CheckOpcode<[ADDXrx64, ADDSXrx64,
+def IsArithExtOp           : CheckOpcode<[ADDWrx, ADDXrx, ADDSWrx, ADDSXrx,
+                                          SUBWrx, SUBXrx, SUBSWrx, SUBSXrx,
+                                          ADDXrx64, ADDSXrx64,
                                           SUBXrx64, SUBSXrx64]>;
-def IsArithExtOp           : CheckOpcode<!listconcat(IsArithExt32Op.ValidOpcodes,
-                                                     IsArithExt64Op.ValidOpcodes)>;
 
 // Identify arithmetic immediate instructions.
 def IsArithImmOp           : CheckOpcode<[ADDWri, ADDXri, ADDSWri, ADDSXri,