[llvm] r349166 - [AArch64] make test immune to scalarization improvements; NFC

[Sanjay Patel via llvm-commits]

Author: spatel
Date: Fri Dec 14 09:44:07 2018
New Revision: 349166

URL: http://llvm.org/viewvc/llvm-project?rev=349166&view=rev
Log:
[AArch64] make test immune to scalarization improvements; NFC

This is explicitly implementing what the comment says rather
than relying on the implicit zext of a costant operand.

Modified:
    llvm/trunk/test/CodeGen/AArch64/aarch64-smull.ll

Modified: llvm/trunk/test/CodeGen/AArch64/aarch64-smull.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/aarch64-smull.ll?rev=349166&r1=349165&r2=349166&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/aarch64-smull.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/aarch64-smull.ll Fri Dec 14 09:44:07 2018
@@ -291,15 +291,16 @@ define <2 x i64> @umull_extvec_v2i32_v2i
   ret <2 x i64> %tmp4
 }
 
-define i16 @smullWithInconsistentExtensions(<8 x i8> %vec) {
+define i16 @smullWithInconsistentExtensions(<8 x i8> %x, <8 x i8> %y) {
 ; If one operand has a zero-extend and the other a sign-extend, smull
 ; cannot be used.
 ; CHECK-LABEL: smullWithInconsistentExtensions:
 ; CHECK: mul {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
-  %1 = sext <8 x i8> %vec to <8 x i16>
-  %2 = mul <8 x i16> %1, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
-  %3 = extractelement <8 x i16> %2, i32 0
-  ret i16 %3
+  %s = sext <8 x i8> %x to <8 x i16>
+  %z = zext <8 x i8> %y to <8 x i16>
+  %m = mul <8 x i16> %s, %z
+  %r = extractelement <8 x i16> %m, i32 0
+  ret i16 %r
 }
 
 define void @distribute(i16* %dst, i8* %src, i32 %mul) nounwind {