[llvm] r349143 - [ARM GlobalISel] Minor refactoring. NFCI
Diana Picus via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 14 04:37:24 PST 2018
Author: rovka
Date: Fri Dec 14 04:37:24 2018
New Revision: 349143
URL: http://llvm.org/viewvc/llvm-project?rev=349143&view=rev
Log:
[ARM GlobalISel] Minor refactoring. NFCI
Refactor the ARMInstructionSelector to cache some opcodes in the
constructor instead of checking all the time if we're in ARM or Thumb
mode.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp?rev=349143&r1=349142&r2=349143&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp Fri Dec 14 04:37:24 2018
@@ -76,6 +76,42 @@ private:
const ARMRegisterBankInfo &RBI;
const ARMSubtarget &STI;
+ // Store the opcodes that we might need, so we don't have to check what kind
+ // of subtarget (ARM vs Thumb) we have all the time.
+ struct OpcodeCache {
+ unsigned ZEXT16;
+ unsigned SEXT16;
+
+ unsigned ZEXT8;
+ unsigned SEXT8;
+
+ // Used for implementing ZEXT/SEXT from i1
+ unsigned AND;
+ unsigned RSB;
+
+ unsigned STORE32;
+ unsigned LOAD32;
+
+ unsigned STORE16;
+ unsigned LOAD16;
+
+ unsigned STORE8;
+ unsigned LOAD8;
+
+ OpcodeCache(const ARMSubtarget &STI);
+ } const Opcodes;
+
+ // Select the opcode for simple extensions (that translate to a single SXT/UXT
+ // instruction). Extension operations more complicated than that should not
+ // invoke this. Returns the original opcode if it doesn't know how to select a
+ // better one.
+ unsigned selectSimpleExtOpc(unsigned Opc, unsigned Size) const;
+
+ // Select the opcode for simple loads and stores. Returns the original opcode
+ // if it doesn't know how to select a better one.
+ unsigned selectLoadStoreOpCode(unsigned Opc, unsigned RegBank,
+ unsigned Size) const;
+
#define GET_GLOBALISEL_PREDICATES_DECL
#include "ARMGenGlobalISel.inc"
#undef GET_GLOBALISEL_PREDICATES_DECL
@@ -107,7 +143,7 @@ ARMInstructionSelector::ARMInstructionSe
const ARMSubtarget &STI,
const ARMRegisterBankInfo &RBI)
: InstructionSelector(), TII(*STI.getInstrInfo()),
- TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI),
+ TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI), Opcodes(STI),
#define GET_GLOBALISEL_PREDICATES_INIT
#include "ARMGenGlobalISel.inc"
#undef GET_GLOBALISEL_PREDICATES_INIT
@@ -225,56 +261,63 @@ static bool selectUnmergeValues(MachineI
return true;
}
-/// Select the opcode for simple extensions (that translate to a single SXT/UXT
-/// instruction). Extension operations more complicated than that should not
-/// invoke this. Returns the original opcode if it doesn't know how to select a
-/// better one.
-static unsigned selectSimpleExtOpc(unsigned Opc, unsigned Size, bool isThumb) {
+ARMInstructionSelector::OpcodeCache::OpcodeCache(const ARMSubtarget &STI) {
+ bool isThumb = STI.isThumb();
+
+ using namespace TargetOpcode;
+
+#define STORE_OPCODE(VAR, OPC) VAR = isThumb ? ARM::t2##OPC : ARM::OPC
+ STORE_OPCODE(SEXT16, SXTH);
+ STORE_OPCODE(ZEXT16, UXTH);
+
+ STORE_OPCODE(SEXT8, SXTB);
+ STORE_OPCODE(ZEXT8, UXTB);
+
+ STORE_OPCODE(AND, ANDri);
+ STORE_OPCODE(RSB, RSBri);
+
+ STORE_OPCODE(STORE32, STRi12);
+ STORE_OPCODE(LOAD32, LDRi12);
+
+ // LDRH/STRH are special...
+ STORE16 = isThumb ? ARM::t2STRHi12 : ARM::STRH;
+ LOAD16 = isThumb ? ARM::t2LDRHi12 : ARM::LDRH;
+
+ STORE_OPCODE(STORE8, STRBi12);
+ STORE_OPCODE(LOAD8, LDRBi12);
+#undef MAP_OPCODE
+}
+
+unsigned ARMInstructionSelector::selectSimpleExtOpc(unsigned Opc,
+ unsigned Size) const {
using namespace TargetOpcode;
if (Size != 8 && Size != 16)
return Opc;
if (Opc == G_SEXT)
- return isThumb ? Size == 8 ? ARM::t2SXTB : ARM::t2SXTH
- : Size == 8 ? ARM::SXTB : ARM::SXTH;
+ return Size == 8 ? Opcodes.SEXT8 : Opcodes.SEXT16;
if (Opc == G_ZEXT)
- return isThumb ? Size == 8 ? ARM::t2UXTB : ARM::t2UXTH
- : Size == 8 ? ARM::UXTB : ARM::UXTH;
+ return Size == 8 ? Opcodes.ZEXT8 : Opcodes.ZEXT16;
return Opc;
}
-/// Select the opcode for simple loads and stores. For types smaller than 32
-/// bits, the value will be zero extended. Returns the original opcode if it
-/// doesn't know how to select a better one.
-static unsigned selectLoadStoreOpCode(unsigned Opc, unsigned RegBank,
- unsigned Size, bool isThumb) {
+unsigned ARMInstructionSelector::selectLoadStoreOpCode(unsigned Opc,
+ unsigned RegBank,
+ unsigned Size) const {
bool isStore = Opc == TargetOpcode::G_STORE;
if (RegBank == ARM::GPRRegBankID) {
- if (isThumb)
- switch (Size) {
- case 1:
- case 8:
- return isStore ? ARM::t2STRBi12 : ARM::t2LDRBi12;
- case 16:
- return isStore ? ARM::t2STRHi12 : ARM::t2LDRHi12;
- case 32:
- return isStore ? ARM::t2STRi12 : ARM::t2LDRi12;
- default:
- return Opc;
- }
-
switch (Size) {
case 1:
case 8:
- return isStore ? ARM::STRBi12 : ARM::LDRBi12;
+ return isStore ? Opcodes.STORE8 : Opcodes.LOAD8;
case 16:
- return isStore ? ARM::STRH : ARM::LDRH;
+ return isStore ? Opcodes.STORE16 : Opcodes.LOAD16;
case 32:
- return isStore ? ARM::STRi12 : ARM::LDRi12;
+ return isStore ? Opcodes.STORE32 : Opcodes.LOAD32;
default:
return Opc;
}
@@ -717,7 +760,7 @@ bool ARMInstructionSelector::select(Mach
switch (SrcSize) {
case 1: {
// ZExt boils down to & 0x1; for SExt we also subtract that from 0
- I.setDesc(TII.get(STI.isThumb() ? ARM::t2ANDri : ARM::ANDri));
+ I.setDesc(TII.get(Opcodes.AND));
MIB.addImm(1).add(predOps(ARMCC::AL)).add(condCodeOp());
if (isSExt) {
@@ -728,13 +771,13 @@ bool ARMInstructionSelector::select(Mach
I.getOperand(0).setReg(AndResult);
auto InsertBefore = std::next(I.getIterator());
- auto SubI = BuildMI(MBB, InsertBefore, I.getDebugLoc(),
- TII.get(STI.isThumb() ? ARM::t2RSBri : ARM::RSBri))
- .addDef(SExtResult)
- .addUse(AndResult)
- .addImm(0)
- .add(predOps(ARMCC::AL))
- .add(condCodeOp());
+ auto SubI =
+ BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(Opcodes.RSB))
+ .addDef(SExtResult)
+ .addUse(AndResult)
+ .addImm(0)
+ .add(predOps(ARMCC::AL))
+ .add(condCodeOp());
if (!constrainSelectedInstRegOperands(*SubI, TII, TRI, RBI))
return false;
}
@@ -742,8 +785,7 @@ bool ARMInstructionSelector::select(Mach
}
case 8:
case 16: {
- unsigned NewOpc =
- selectSimpleExtOpc(I.getOpcode(), SrcSize, STI.isThumb());
+ unsigned NewOpc = selectSimpleExtOpc(I.getOpcode(), SrcSize);
if (NewOpc == I.getOpcode())
return false;
I.setDesc(TII.get(NewOpc));
@@ -917,8 +959,7 @@ bool ARMInstructionSelector::select(Mach
assert((ValSize != 64 || STI.hasVFP2()) &&
"Don't know how to load/store 64-bit value without VFP");
- const auto NewOpc =
- selectLoadStoreOpCode(I.getOpcode(), RegBank, ValSize, STI.isThumb());
+ const auto NewOpc = selectLoadStoreOpCode(I.getOpcode(), RegBank, ValSize);
if (NewOpc == G_LOAD || NewOpc == G_STORE)
return false;
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