[PATCH] D55600: [TargetLowering] Add ISD::OR + ISD::XOR handling to SimplifyDemandedVectorElts

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon updated this revision to Diff 178087.
RKSimon added a comment.

rebase


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D55600/new/

https://reviews.llvm.org/D55600

Files:
  lib/CodeGen/SelectionDAG/TargetLowering.cpp
  test/CodeGen/SystemZ/knownbits.ll
  test/CodeGen/X86/bitcast-and-setcc-128.ll
  test/CodeGen/X86/bitcast-and-setcc-256.ll
  test/CodeGen/X86/bitcast-setcc-128.ll
  test/CodeGen/X86/bitcast-setcc-256.ll
  test/CodeGen/X86/combine-sdiv.ll
  test/CodeGen/X86/copysign-constant-magnitude.ll
  test/CodeGen/X86/fp128-cast.ll
  test/CodeGen/X86/known-bits-vector.ll
  test/CodeGen/X86/known-signbits-vector.ll
  test/CodeGen/X86/movmsk-cmp.ll
  test/CodeGen/X86/packss.ll
  test/CodeGen/X86/psubus.ll
  test/CodeGen/X86/sat-add.ll
  test/CodeGen/X86/vec_minmax_sint.ll
  test/CodeGen/X86/vec_minmax_uint.ll
  test/CodeGen/X86/vector-reduce-smax-widen.ll
  test/CodeGen/X86/vector-reduce-smax.ll
  test/CodeGen/X86/vector-reduce-smin-widen.ll
  test/CodeGen/X86/vector-reduce-smin.ll
  test/CodeGen/X86/vector-reduce-umax-widen.ll
  test/CodeGen/X86/vector-reduce-umax.ll
  test/CodeGen/X86/vector-reduce-umin-widen.ll
  test/CodeGen/X86/vector-reduce-umin.ll
  test/CodeGen/X86/vector-trunc-packus-widen.ll
  test/CodeGen/X86/vector-trunc-packus.ll
  test/CodeGen/X86/vector-trunc-ssat-widen.ll
  test/CodeGen/X86/vector-trunc-ssat.ll
  test/CodeGen/X86/vector-trunc-usat-widen.ll
  test/CodeGen/X86/vector-trunc-usat.ll

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