[llvm] r349014 - AMDGPU/GlobalISel: Legalize f64 fadd/fmul

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Thu Dec 13 00:27:48 2018
New Revision: 349014

URL: http://llvm.org/viewvc/llvm-project?rev=349014&view=rev
Log:
AMDGPU/GlobalISel: Legalize f64 fadd/fmul

Modified:
    llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
    llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir

Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp?rev=349014&r1=349013&r2=349014&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp Thu Dec 13 00:27:48 2018
@@ -88,14 +88,14 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo
   // between these two scenarios.
   setAction({G_CONSTANT, S1}, Legal);
 
-  setAction({G_FADD, S32}, Legal);
+  getActionDefinitionsBuilder(
+    { G_FADD, G_FMUL })
+    .legalFor({S32, S64});
 
   setAction({G_FCMP, S1}, Legal);
   setAction({G_FCMP, 1, S32}, Legal);
   setAction({G_FCMP, 1, S64}, Legal);
 
-  setAction({G_FMUL, S32}, Legal);
-
   setAction({G_ZEXT, S64}, Legal);
   setAction({G_ZEXT, 1, S32}, Legal);
 

Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir?rev=349014&r1=349013&r2=349014&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir Thu Dec 13 00:27:48 2018
@@ -1,7 +1,7 @@
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -run-pass=legalizer %s -o - | FileCheck %s
 
 ---
-name:            test_fadd
+name: test_fadd_f32
 body: |
   bb.0.entry:
     liveins: $vgpr0, $vgpr1
@@ -13,3 +13,14 @@ body: |
     %2:_(s32) = G_FADD %0, %1
     $vgpr0 = COPY %2
 ...
+---
+name: test_fadd_f64
+body: |
+  bb.0.entry:
+    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+    %0:_(s64) = COPY $vgpr0_vgpr1
+    %1:_(s64) = COPY $vgpr2_vgpr3
+    %2:_(s64) = G_FADD %0, %1
+    $vgpr0_vgpr1 = COPY %2
+...

Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir?rev=349014&r1=349013&r2=349014&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir Thu Dec 13 00:27:48 2018
@@ -2,7 +2,7 @@
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
 
 ---
-name:            test_fmul
+name: test_fmul_f32
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
@@ -16,3 +16,18 @@ body: |
     %2:_(s32) = G_FMUL %0, %1
     $vgpr0 = COPY %2
 ...
+---
+name: test_fmul_f64
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+    ; CHECK-LABEL: name: test_fmul
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
+    ; CHECK: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[COPY1]]
+    %0:_(s64) = COPY $vgpr0_vgpr1
+    %1:_(s64) = COPY $vgpr2_vgpr3
+    %2:_(s64) = G_FMUL %0, %1
+    $vgpr0_vgpr1 = COPY %2
+...