[llvm] r349011 - AMDGPU/GlobalISel: Test cleanups
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 13 00:11:45 PST 2018
Author: arsenm
Date: Thu Dec 13 00:11:45 2018
New Revision: 349011
URL: http://llvm.org/viewvc/llvm-project?rev=349011&view=rev
Log:
AMDGPU/GlobalISel: Test cleanups
Remove IR and registers sections
Modified:
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir?rev=349011&r1=349010&r2=349011&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir Thu Dec 13 00:11:45 2018
@@ -1,16 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
---- |
- define void @test_add() { ret void }
-...
-
---
name: test_add
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: _ }
body: |
bb.0:
liveins: $vgpr0, $vgpr1
@@ -19,8 +11,8 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
- %0(s32) = COPY $vgpr0
- %1(s32) = COPY $vgpr1
- %2(s32) = G_ADD %0, %1
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s32) = G_ADD %0, %1
$vgpr0 = COPY %2
...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir?rev=349011&r1=349010&r2=349011&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir Thu Dec 13 00:11:45 2018
@@ -1,16 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
---- |
- define void @test_and() { ret void }
-...
-
---
name: test_and
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: _ }
body: |
bb.0:
liveins: $vgpr0, $vgpr1
@@ -19,8 +11,8 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY1]]
- %0(s32) = COPY $vgpr0
- %1(s32) = COPY $vgpr1
- %2(s32) = G_AND %0, %1
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s32) = G_AND %0, %1
$vgpr0 = COPY %2
...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir?rev=349011&r1=349010&r2=349011&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir Thu Dec 13 00:11:45 2018
@@ -3,10 +3,6 @@
---
name: test_ashr
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: _ }
body: |
bb.0.entry:
liveins: $vgpr0, $vgpr1
@@ -15,8 +11,8 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]]
- %0(s32) = COPY $vgpr0
- %1(s32) = COPY $vgpr1
- %2(s32) = G_ASHR %0, %1
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s32) = G_ASHR %0, %1
$vgpr0 = COPY %2
...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir?rev=349011&r1=349010&r2=349011&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir Thu Dec 13 00:11:45 2018
@@ -1,16 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
---- |
- define void @test_bitcast() { ret void }
-...
-
---
name: test_bitcast
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: _ }
body: |
bb.0:
liveins: $vgpr0
@@ -19,8 +11,8 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY]](s32)
; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[BITCAST]](<2 x s16>)
- %0(s32) = COPY $vgpr0
- %1(<2 x s16>) = G_BITCAST %0
- %2(s32) = G_BITCAST %1
+ %0:_(s32) = COPY $vgpr0
+ %1:_(<2 x s16>) = G_BITCAST %0
+ %2:_(s32) = G_BITCAST %1
$vgpr0 = COPY %2
...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir?rev=349011&r1=349010&r2=349011&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir Thu Dec 13 00:11:45 2018
@@ -1,27 +1,15 @@
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -run-pass=legalizer %s -o - | FileCheck %s
---- |
- define void @test_fadd() {
- entry:
- ret void
- }
-
-...
-
---
name: test_fadd
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: _ }
body: |
bb.0.entry:
liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: test_fadd
; CHECK: %2:_(s32) = G_FADD %0, %1
- %0(s32) = COPY $vgpr0
- %1(s32) = COPY $vgpr1
- %2(s32) = G_FADD %0, %1
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s32) = G_FADD %0, %1
$vgpr0 = COPY %2
...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir?rev=349011&r1=349010&r2=349011&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir Thu Dec 13 00:11:45 2018
@@ -3,33 +3,25 @@
---
name: test_fcmp_f32
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: _ }
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_fcmp_f32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- %0(s32) = G_CONSTANT i32 0
- %1(s32) = COPY $vgpr0
+ %0:_(s32) = G_CONSTANT i32 0
+ %1:_(s32) = COPY $vgpr0
- %2(s1) = G_FCMP floatpred(uge), %0, %1
+ %2:_(s1) = G_FCMP floatpred(uge), %0, %1
...
---
name: test_fcmp_f64
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: _ }
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_fcmp_f64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- %0(s64) = G_CONSTANT i64 0
- %1(s64) = COPY $vgpr0_vgpr1
+ %0:_(s64) = G_CONSTANT i64 0
+ %1:_(s64) = COPY $vgpr0_vgpr1
- %2(s1) = G_FCMP floatpred(uge), %0, %1
+ %2:_(s1) = G_FCMP floatpred(uge), %0, %1
...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir?rev=349011&r1=349010&r2=349011&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir Thu Dec 13 00:11:45 2018
@@ -1,16 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
---- |
- define void @test_fmul() { ret void }
-...
-
---
name: test_fmul
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: _ }
body: |
bb.0:
liveins: $vgpr0, $vgpr1
@@ -19,8 +11,8 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[COPY1]]
- %0(s32) = COPY $vgpr0
- %1(s32) = COPY $vgpr1
- %2(s32) = G_FMUL %0, %1
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s32) = G_FMUL %0, %1
$vgpr0 = COPY %2
...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir?rev=349011&r1=349010&r2=349011&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir Thu Dec 13 00:11:45 2018
@@ -1,22 +1,14 @@
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -run-pass=legalizer %s -o - | FileCheck %s
---- |
- define void @test_fptoui() { ret void }
-...
-
---
name: test_fptoui
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: _ }
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_fptoui
; CHECK: %1:_(s32) = G_FPTOUI %0
- %0(s32) = COPY $vgpr0
- %1(s32) = G_FPTOUI %0
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = G_FPTOUI %0
$vgpr0 = COPY %1
...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir?rev=349011&r1=349010&r2=349011&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir Thu Dec 13 00:11:45 2018
@@ -1,19 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -march=amdgcn -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
---- |
- define void @test_icmp() {
- entry:
- ret void
- }
-...
-
---
name: test_icmp
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: _ }
body: |
bb.0.entry:
liveins: $vgpr0
@@ -23,9 +12,9 @@ body: |
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C]], [[COPY]]
; CHECK: $vgpr0 = COPY [[SELECT]](s32)
- %0(s32) = G_CONSTANT i32 0
- %1(s32) = COPY $vgpr0
- %2(s1) = G_ICMP intpred(ne), %0, %1
+ %0:_(s32) = G_CONSTANT i32 0
+ %1:_(s32) = COPY $vgpr0
+ %2:_(s1) = G_ICMP intpred(ne), %0, %1
%3:_(s32) = G_SELECT %2(s1), %0(s32), %1(s32)
$vgpr0 = COPY %3
...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir?rev=349011&r1=349010&r2=349011&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir Thu Dec 13 00:11:45 2018
@@ -1,15 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
---- |
- define void @test_or() { ret void }
-...
---
name: test_or
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: _ }
body: |
bb.0:
liveins: $vgpr0, $vgpr1
@@ -18,8 +11,8 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[COPY1]]
- %0(s32) = COPY $vgpr0
- %1(s32) = COPY $vgpr1
- %2(s32) = G_OR %0, %1
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s32) = G_OR %0, %1
$vgpr0 = COPY %2
...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir?rev=349011&r1=349010&r2=349011&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir Thu Dec 13 00:11:45 2018
@@ -1,19 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -march=amdgcn -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
---- |
- define void @test_select() { ret void }
-...
-
---
name: test_select
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: _ }
- - { id: 3, class: _ }
- - { id: 4, class: _ }
- - { id: 5, class: _ }
body: |
bb.0:
liveins: $vgpr0
@@ -24,13 +13,13 @@ body: |
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[C2]]
- %0(s32) = G_CONSTANT i32 0
- %1(s32) = COPY $vgpr0
+ %0:_(s32) = G_CONSTANT i32 0
+ %1:_(s32) = COPY $vgpr0
- %2(s1) = G_ICMP intpred(ne), %0, %1
- %3(s32) = G_CONSTANT i32 1
- %4(s32) = G_CONSTANT i32 2
- %5(s32) = G_SELECT %2, %3, %4
+ %2:_(s1) = G_ICMP intpred(ne), %0, %1
+ %3:_(s32) = G_CONSTANT i32 1
+ %4:_(s32) = G_CONSTANT i32 2
+ %5:_(s32) = G_SELECT %2, %3, %4
$vgpr0 = COPY %5
...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir?rev=349011&r1=349010&r2=349011&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir Thu Dec 13 00:11:45 2018
@@ -3,10 +3,6 @@
---
name: test_shl
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: _ }
body: |
bb.0.entry:
liveins: $vgpr0, $vgpr1
@@ -15,8 +11,8 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]]
- %0(s32) = COPY $vgpr0
- %1(s32) = COPY $vgpr1
- %2(s32) = G_SHL %0, %1
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s32) = G_SHL %0, %1
$vgpr0 = COPY %2
...
More information about the llvm-commits
mailing list