[PATCH] D55600: [TargetLowering] Add ISD::OR + ISD::XOR handling to SimplifyDemandedVectorElts

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: jonpa, andreadb, spatel, craig.topper.

@jonpa Without the change to knownbits.ll then the TM instruction reappears contrary to the comment - is this OK?


Repository:
  rL LLVM

https://reviews.llvm.org/D55600

Files:
  lib/CodeGen/SelectionDAG/TargetLowering.cpp
  test/CodeGen/SystemZ/knownbits.ll
  test/CodeGen/X86/bitcast-and-setcc-128.ll
  test/CodeGen/X86/bitcast-and-setcc-256.ll
  test/CodeGen/X86/bitcast-setcc-128.ll
  test/CodeGen/X86/bitcast-setcc-256.ll
  test/CodeGen/X86/combine-sdiv.ll
  test/CodeGen/X86/copysign-constant-magnitude.ll
  test/CodeGen/X86/fp128-cast.ll
  test/CodeGen/X86/known-bits-vector.ll
  test/CodeGen/X86/known-signbits-vector.ll
  test/CodeGen/X86/movmsk-cmp.ll
  test/CodeGen/X86/packss.ll
  test/CodeGen/X86/psubus.ll
  test/CodeGen/X86/sat-add.ll
  test/CodeGen/X86/vec_minmax_sint.ll
  test/CodeGen/X86/vec_minmax_uint.ll
  test/CodeGen/X86/vector-reduce-smax-widen.ll
  test/CodeGen/X86/vector-reduce-smax.ll
  test/CodeGen/X86/vector-reduce-smin-widen.ll
  test/CodeGen/X86/vector-reduce-smin.ll
  test/CodeGen/X86/vector-reduce-umax-widen.ll
  test/CodeGen/X86/vector-reduce-umax.ll
  test/CodeGen/X86/vector-reduce-umin-widen.ll
  test/CodeGen/X86/vector-reduce-umin.ll
  test/CodeGen/X86/vector-trunc-packus-widen.ll
  test/CodeGen/X86/vector-trunc-packus.ll
  test/CodeGen/X86/vector-trunc-ssat-widen.ll
  test/CodeGen/X86/vector-trunc-ssat.ll
  test/CodeGen/X86/vector-trunc-usat-widen.ll
  test/CodeGen/X86/vector-trunc-usat.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D55600.177851.patch
Type: text/x-patch
Size: 352331 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20181212/82a65bc1/attachment-0001.bin>