[llvm] r348802 - [Hexagon] Couple of fixes in optimize addressing mode

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Mon Dec 10 13:56:04 2018
New Revision: 348802

URL: http://llvm.org/viewvc/llvm-project?rev=348802&view=rev
Log:
[Hexagon] Couple of fixes in optimize addressing mode

- Check if an operand is an immediate before calling getImm. Some operands
  that take constant values can actually have global symbols or other
  constant expressions.
- When a load-constant instruction can be folded into users, make sure to
  only delete it when all users have been successfully converted.

Added:
    llvm/trunk/test/CodeGen/Hexagon/addrmode-immop.mir
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp?rev=348802&r1=348801&r2=348802&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp Mon Dec 10 13:56:04 2018
@@ -502,7 +502,8 @@ bool HexagonOptAddrMode::changeLoad(Mach
       MIB.add(ImmOp);
       OpStart = 4;
       Changed = true;
-    } else if (HII->getAddrMode(*OldMI) == HexagonII::BaseImmOffset) {
+    } else if (HII->getAddrMode(*OldMI) == HexagonII::BaseImmOffset &&
+               OldMI->getOperand(2).isImm()) {
       short NewOpCode = HII->changeAddrMode_io_abs(*OldMI);
       assert(NewOpCode >= 0 && "Invalid New opcode\n");
       MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode))
@@ -518,17 +519,19 @@ bool HexagonOptAddrMode::changeLoad(Mach
 
     LLVM_DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
     LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n");
-  } else if (ImmOpNum == 2 && OldMI->getOperand(3).getImm() == 0) {
-    short NewOpCode = HII->changeAddrMode_rr_io(*OldMI);
-    assert(NewOpCode >= 0 && "Invalid New opcode\n");
-    MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
-    MIB.add(OldMI->getOperand(0));
-    MIB.add(OldMI->getOperand(1));
-    MIB.add(ImmOp);
-    OpStart = 4;
-    Changed = true;
-    LLVM_DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
-    LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n");
+  } else if (ImmOpNum == 2) {
+    if (OldMI->getOperand(3).isImm() && OldMI->getOperand(3).getImm() == 0) {
+      short NewOpCode = HII->changeAddrMode_rr_io(*OldMI);
+      assert(NewOpCode >= 0 && "Invalid New opcode\n");
+      MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
+      MIB.add(OldMI->getOperand(0));
+      MIB.add(OldMI->getOperand(1));
+      MIB.add(ImmOp);
+      OpStart = 4;
+      Changed = true;
+      LLVM_DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
+      LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n");
+    }
   }
 
   if (Changed)
@@ -758,11 +761,13 @@ bool HexagonOptAddrMode::processBlock(No
       // This could happen, for example, when DefR = R4, but the used
       // register is D2.
 
+      // Change UseMI if replacement is possible. If any replacement failed,
+      // or wasn't attempted, make sure to keep the TFR.
+      bool Xformed = false;
       if (UseMOnum >= 0 && InstrEvalResult[UseMI])
-        // Change UseMI if replacement is possible.
-        Changed |= xformUseMI(MI, UseMI, UseN, UseMOnum);
-      else
-        KeepTfr = true;
+        Xformed = xformUseMI(MI, UseMI, UseN, UseMOnum);
+      Changed |=  Xformed;
+      KeepTfr |= !Xformed;
     }
     if (!KeepTfr)
       Deleted.insert(MI);

Added: llvm/trunk/test/CodeGen/Hexagon/addrmode-immop.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/addrmode-immop.mir?rev=348802&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/addrmode-immop.mir (added)
+++ llvm/trunk/test/CodeGen/Hexagon/addrmode-immop.mir Mon Dec 10 13:56:04 2018
@@ -0,0 +1,40 @@
+# RUN: llc -march=hexagon -run-pass amode-opt -verify-machineinstrs %s -o - | FileCheck %s
+# REQUIRES: asserts
+
+# Check that this doesn't crash.
+# CHECK: $r2 = L2_loadri_io killed $r2, @f1 - 1
+
+--- |
+  target triple = "hexagon-unknown-unknown-elf"
+
+  %s.0 = type { i32 (...)**, i32, i32, %s.1 }
+  %s.1 = type { i32, i32 }
+
+  @g0 = external dso_local unnamed_addr constant { [3 x i8*], [3 x i8*] }, align 4
+
+  ; Function Attrs: norecurse
+  define void @f0() #0 {
+  b0:
+    %v0 = load i32 (%s.0*)*, i32 (%s.0*)** bitcast (i8* getelementptr (i8, i8* bitcast (i8** getelementptr inbounds ({ [3 x i8*], [3 x i8*] }, { [3 x i8*], [3 x i8*] }* @g0, i32 0, inrange i32 0, i32 3) to i8*), i32 sub (i32 ptrtoint (i32 (%s.0*)* @f1 to i32), i32 1)) to i32 (%s.0*)**), align 4
+    %v1 = call i32 %v0(%s.0* nonnull undef)
+    unreachable
+  }
+
+  ; Function Attrs: norecurse nounwind
+  declare dso_local i32 @f1(%s.0*) #1 align 2
+
+  attributes #0 = { norecurse "target-cpu"="hexagonv60" }
+  attributes #1 = { norecurse nounwind "target-cpu"="hexagonv60" }
+...
+
+---
+name: f0
+tracksRegLiveness: true
+body: |
+  bb.0.b0:
+    $r2 = A2_tfrsi @g0 + 12
+    $r2 = L2_loadri_io killed $r2, @f1 - 1 :: (load 4 from `i32 (%s.0*)** bitcast (i8* getelementptr (i8, i8* bitcast (i8** getelementptr inbounds ({ [3 x i8*], [3 x i8*] }, { [3 x i8*], [3 x i8*] }* @g0, i32 0, inrange i32 0, i32 3) to i8*), i32 sub (i32 ptrtoint (i32 (%s.0*)* @f1 to i32), i32 1)) to i32 (%s.0*)**)`)
+    ADJCALLSTACKDOWN 0, 0, implicit-def $r29, implicit-def dead $r30, implicit $r31, implicit $r30, implicit $r29
+    PS_callr_nr killed $r2, hexagoncsr, implicit undef $r0, implicit-def $r29, implicit-def dead $r0
+    ADJCALLSTACKUP 0, 0, implicit-def dead $r29, implicit-def dead $r30, implicit-def dead $r31, implicit $r29
+...