[llvm] r348737 - [X86] Merge addcarryx/addcarry intrinsic into a single addcarry intrinsic.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Dec 9 22:07:50 PST 2018
Author: ctopper
Date: Sun Dec 9 22:07:50 2018
New Revision: 348737
URL: http://llvm.org/viewvc/llvm-project?rev=348737&view=rev
Log:
[X86] Merge addcarryx/addcarry intrinsic into a single addcarry intrinsic.
Both intrinsics do the exact same thing so we really only need one.
Earlier in the 8.0 cycle we changed the signature of this intrinsic without renaming it. But it looks difficult to get the autoupgrade code to allow me to merge the intrinsics and change the signature at the same time. So I've renamed the intrinsic slightly for the new merged intrinsic. I'm skipping autoupgrading from the previous new to 8.0 signature. I've also renamed the subborrow for consistency.
Modified:
llvm/trunk/include/llvm/IR/IntrinsicsX86.td
llvm/trunk/lib/IR/AutoUpgrade.cpp
llvm/trunk/lib/Target/X86/X86IntrinsicsInfo.h
llvm/trunk/test/CodeGen/X86/adx-commute.mir
llvm/trunk/test/CodeGen/X86/adx-intrinsics.ll
llvm/trunk/test/CodeGen/X86/stack-folding-adx-x86_64.ll
llvm/trunk/test/CodeGen/X86/stack-folding-adx.mir
Modified: llvm/trunk/include/llvm/IR/IntrinsicsX86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsX86.td?rev=348737&r1=348736&r2=348737&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IR/IntrinsicsX86.td (original)
+++ llvm/trunk/include/llvm/IR/IntrinsicsX86.td Sun Dec 9 22:07:50 2018
@@ -2726,22 +2726,16 @@ let TargetPrefix = "x86" in { // All in
// ADX
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
- def int_x86_addcarryx_u32:
+ def int_x86_addcarry_32:
Intrinsic<[llvm_i8_ty, llvm_i32_ty],
[llvm_i8_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
- def int_x86_addcarryx_u64:
+ def int_x86_addcarry_64:
Intrinsic<[llvm_i8_ty, llvm_i64_ty],
[llvm_i8_ty, llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
- def int_x86_addcarry_u32:
+ def int_x86_subborrow_32:
Intrinsic<[llvm_i8_ty, llvm_i32_ty],
[llvm_i8_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
- def int_x86_addcarry_u64:
- Intrinsic<[llvm_i8_ty, llvm_i64_ty],
- [llvm_i8_ty, llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
- def int_x86_subborrow_u32:
- Intrinsic<[llvm_i8_ty, llvm_i32_ty],
- [llvm_i8_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
- def int_x86_subborrow_u64:
+ def int_x86_subborrow_64:
Intrinsic<[llvm_i8_ty, llvm_i64_ty],
[llvm_i8_ty, llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
}
Modified: llvm/trunk/lib/IR/AutoUpgrade.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/AutoUpgrade.cpp?rev=348737&r1=348736&r2=348737&view=diff
==============================================================================
--- llvm/trunk/lib/IR/AutoUpgrade.cpp (original)
+++ llvm/trunk/lib/IR/AutoUpgrade.cpp Sun Dec 9 22:07:50 2018
@@ -65,24 +65,19 @@ static bool UpgradeX86IntrinsicsWith8Bit
return true;
}
-static bool UpgradeADCSBBIntrinsic(Function *F, Intrinsic::ID IID,
- Function *&NewFn) {
- // If this intrinsic has 3 operands, it's the new version.
- if (F->getFunctionType()->getNumParams() == 3)
- return false;
-
- rename(F);
- NewFn = Intrinsic::getDeclaration(F->getParent(), IID);
- return true;
-}
-
static bool ShouldUpgradeX86Intrinsic(Function *F, StringRef Name) {
// All of the intrinsics matches below should be marked with which llvm
// version started autoupgrading them. At some point in the future we would
// like to use this information to remove upgrade code for some older
// intrinsics. It is currently undecided how we will determine that future
// point.
- if (Name.startswith("sse2.paddus.") || // Added in 8.0
+ if (Name == "addcarryx.u32" || // Added in 8.0
+ Name == "addcarryx.u64" || // Added in 8.0
+ Name == "addcarry.u32" || // Added in 8.0
+ Name == "addcarry.u64" || // Added in 8.0
+ Name == "subborrow.u32" || // Added in 8.0
+ Name == "subborrow.u64" || // Added in 8.0
+ Name.startswith("sse2.paddus.") || // Added in 8.0
Name.startswith("sse2.psubus.") || // Added in 8.0
Name.startswith("avx2.paddus.") || // Added in 8.0
Name.startswith("avx2.psubus.") || // Added in 8.0
@@ -382,19 +377,6 @@ static bool UpgradeX86IntrinsicFunction(
return true;
}
- if (Name == "addcarryx.u32") // Added in 8.0
- return UpgradeADCSBBIntrinsic(F, Intrinsic::x86_addcarryx_u32, NewFn);
- if (Name == "addcarryx.u64") // Added in 8.0
- return UpgradeADCSBBIntrinsic(F, Intrinsic::x86_addcarryx_u64, NewFn);
- if (Name == "addcarry.u32") // Added in 8.0
- return UpgradeADCSBBIntrinsic(F, Intrinsic::x86_addcarry_u32, NewFn);
- if (Name == "addcarry.u64") // Added in 8.0
- return UpgradeADCSBBIntrinsic(F, Intrinsic::x86_addcarry_u64, NewFn);
- if (Name == "subborrow.u32") // Added in 8.0
- return UpgradeADCSBBIntrinsic(F, Intrinsic::x86_subborrow_u32, NewFn);
- if (Name == "subborrow.u64") // Added in 8.0
- return UpgradeADCSBBIntrinsic(F, Intrinsic::x86_subborrow_u64, NewFn);
-
if (Name == "rdtscp") { // Added in 8.0
// If this intrinsic has 0 operands, it's the new version.
if (F->getFunctionType()->getNumParams() == 0)
@@ -3277,6 +3259,39 @@ void llvm::UpgradeIntrinsicCall(CallInst
Value *PassThru = ZeroMask ? ConstantAggregateZero::get(CI->getType())
: CI->getArgOperand(0);
Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, PassThru);
+ } else if (IsX86 && (Name == "addcarryx.u32" || Name == "addcarryx.u64" ||
+ Name == "addcarry.u32" || Name == "addcarry.u64" ||
+ Name == "subborrow.u32" || Name == "subborrow.u64")) {
+ Intrinsic::ID IID;
+ if (Name[0] == 'a' && Name.back() == '2')
+ IID = Intrinsic::x86_addcarry_32;
+ else if (Name[0] == 'a' && Name.back() == '4')
+ IID = Intrinsic::x86_addcarry_64;
+ else if (Name[0] == 's' && Name.back() == '2')
+ IID = Intrinsic::x86_subborrow_32;
+ else if (Name[0] == 's' && Name.back() == '4')
+ IID = Intrinsic::x86_subborrow_64;
+ else
+ llvm_unreachable("Unexpected intrinsic");
+
+ // Make a call with 3 operands.
+ Value *Args[] = { CI->getArgOperand(0), CI->getArgOperand(1),
+ CI->getArgOperand(2)};
+ Value *NewCall = Builder.CreateCall(
+ Intrinsic::getDeclaration(CI->getModule(), IID),
+ Args);
+
+ // Extract the second result and store it.
+ Value *Data = Builder.CreateExtractValue(NewCall, 1);
+ // Cast the pointer to the right type.
+ Value *Ptr = Builder.CreateBitCast(CI->getArgOperand(3),
+ llvm::PointerType::getUnqual(Data->getType()));
+ Builder.CreateAlignedStore(Data, Ptr, 1);
+ // Replace the original call result with the first result of the new call.
+ Value *CF = Builder.CreateExtractValue(NewCall, 0);
+
+ CI->replaceAllUsesWith(CF);
+ Rep = nullptr;
} else if (IsX86 && Name.startswith("avx512.mask.") &&
upgradeAVX512MaskToSelect(Name, Builder, *CI, Rep)) {
// Rep will be updated by the call in the condition.
@@ -3477,40 +3492,6 @@ void llvm::UpgradeIntrinsicCall(CallInst
CI->eraseFromParent();
return;
}
-
- case Intrinsic::x86_addcarryx_u32:
- case Intrinsic::x86_addcarryx_u64:
- case Intrinsic::x86_addcarry_u32:
- case Intrinsic::x86_addcarry_u64:
- case Intrinsic::x86_subborrow_u32:
- case Intrinsic::x86_subborrow_u64: {
- // This used to take 4 arguments. If we only have 3 arguments its already
- // upgraded.
- if (CI->getNumOperands() == 3)
- return;
-
- // Make a call with 3 operands.
- NewCall = Builder.CreateCall(NewFn, { CI->getArgOperand(0),
- CI->getArgOperand(1),
- CI->getArgOperand(2)});
- // Extract the second result and store it.
- Value *Data = Builder.CreateExtractValue(NewCall, 1);
- // Cast the pointer to the right type.
- Value *Ptr = Builder.CreateBitCast(CI->getArgOperand(3),
- llvm::PointerType::getUnqual(Data->getType()));
- Builder.CreateAlignedStore(Data, Ptr, 1);
- // Replace the original call result with the first result of the new call.
- Value *CF = Builder.CreateExtractValue(NewCall, 0);
-
- std::string Name = CI->getName();
- if (!Name.empty()) {
- CI->setName(Name + ".old");
- NewCall->setName(Name);
- }
- CI->replaceAllUsesWith(CF);
- CI->eraseFromParent();
- return;
- }
case Intrinsic::x86_sse41_insertps:
case Intrinsic::x86_sse41_dppd:
Modified: llvm/trunk/lib/Target/X86/X86IntrinsicsInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86IntrinsicsInfo.h?rev=348737&r1=348736&r2=348737&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86IntrinsicsInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86IntrinsicsInfo.h Sun Dec 9 22:07:50 2018
@@ -286,10 +286,8 @@ static const IntrinsicData* getIntrinsic
* the alphabetical order.
*/
static const IntrinsicData IntrinsicsWithoutChain[] = {
- X86_INTRINSIC_DATA(addcarry_u32, ADX, X86ISD::ADC, X86ISD::ADD),
- X86_INTRINSIC_DATA(addcarry_u64, ADX, X86ISD::ADC, X86ISD::ADD),
- X86_INTRINSIC_DATA(addcarryx_u32, ADX, X86ISD::ADC, X86ISD::ADD),
- X86_INTRINSIC_DATA(addcarryx_u64, ADX, X86ISD::ADC, X86ISD::ADD),
+ X86_INTRINSIC_DATA(addcarry_32, ADX, X86ISD::ADC, X86ISD::ADD),
+ X86_INTRINSIC_DATA(addcarry_64, ADX, X86ISD::ADC, X86ISD::ADD),
X86_INTRINSIC_DATA(avx_addsub_pd_256, INTR_TYPE_2OP, X86ISD::ADDSUB, 0),
X86_INTRINSIC_DATA(avx_addsub_ps_256, INTR_TYPE_2OP, X86ISD::ADDSUB, 0),
X86_INTRINSIC_DATA(avx_cmp_pd_256, INTR_TYPE_3OP, X86ISD::CMPP, 0),
@@ -1223,8 +1221,8 @@ static const IntrinsicData IntrinsicsWi
X86_INTRINSIC_DATA(ssse3_pmadd_ub_sw_128, INTR_TYPE_2OP, X86ISD::VPMADDUBSW, 0),
X86_INTRINSIC_DATA(ssse3_pmul_hr_sw_128, INTR_TYPE_2OP, X86ISD::MULHRS, 0),
X86_INTRINSIC_DATA(ssse3_pshuf_b_128, INTR_TYPE_2OP, X86ISD::PSHUFB, 0),
- X86_INTRINSIC_DATA(subborrow_u32, ADX, X86ISD::SBB, X86ISD::SUB),
- X86_INTRINSIC_DATA(subborrow_u64, ADX, X86ISD::SBB, X86ISD::SUB),
+ X86_INTRINSIC_DATA(subborrow_32, ADX, X86ISD::SBB, X86ISD::SUB),
+ X86_INTRINSIC_DATA(subborrow_64, ADX, X86ISD::SBB, X86ISD::SUB),
X86_INTRINSIC_DATA(tbm_bextri_u32, INTR_TYPE_2OP, X86ISD::BEXTR, 0),
X86_INTRINSIC_DATA(tbm_bextri_u64, INTR_TYPE_2OP, X86ISD::BEXTR, 0),
X86_INTRINSIC_DATA(vcvtph2ps_128, INTR_TYPE_1OP, X86ISD::CVTPH2PS, 0),
Modified: llvm/trunk/test/CodeGen/X86/adx-commute.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/adx-commute.mir?rev=348737&r1=348736&r2=348737&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/adx-commute.mir (original)
+++ llvm/trunk/test/CodeGen/X86/adx-commute.mir Sun Dec 9 22:07:50 2018
@@ -7,7 +7,7 @@
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
define void @adcx32_commute(i8 %cf, i32 %a, i32 %b, i32* %res) #0 {
- %ret = call { i8, i32 } @llvm.x86.addcarryx.u32(i8 %cf, i32 %a, i32 %b)
+ %ret = call { i8, i32 } @llvm.x86.addcarry.32(i8 %cf, i32 %a, i32 %b)
%1 = extractvalue { i8, i32 } %ret, 1
%2 = mul i32 %a, %1
store i32 %2, i32* %res
@@ -15,7 +15,7 @@
}
define void @adcx64_commute(i8 %cf, i64 %a, i64 %b, i64* %res) #0 {
- %ret = call { i8, i64 } @llvm.x86.addcarryx.u64(i8 %cf, i64 %a, i64 %b)
+ %ret = call { i8, i64 } @llvm.x86.addcarry.64(i8 %cf, i64 %a, i64 %b)
%1 = extractvalue { i8, i64 } %ret, 1
%2 = mul i64 %a, %1
store i64 %2, i64* %res
@@ -23,7 +23,7 @@
}
define void @adox32_commute(i8 %cf, i32 %a, i32 %b, i32* %res) #0 {
- %ret = call { i8, i32 } @llvm.x86.addcarryx.u32(i8 %cf, i32 %a, i32 %b)
+ %ret = call { i8, i32 } @llvm.x86.addcarry.32(i8 %cf, i32 %a, i32 %b)
%1 = extractvalue { i8, i32 } %ret, 1
%2 = mul i32 %a, %1
store i32 %2, i32* %res
@@ -31,7 +31,7 @@
}
define void @adox64_commute(i8 %cf, i64 %a, i64 %b, i64* %res) #0 {
- %ret = call { i8, i64 } @llvm.x86.addcarryx.u64(i8 %cf, i64 %a, i64 %b)
+ %ret = call { i8, i64 } @llvm.x86.addcarry.64(i8 %cf, i64 %a, i64 %b)
%1 = extractvalue { i8, i64 } %ret, 1
%2 = mul i64 %a, %1
store i64 %2, i64* %res
@@ -39,10 +39,10 @@
}
; Function Attrs: nounwind readnone
- declare { i8, i32 } @llvm.x86.addcarryx.u32(i8, i32, i32) #1
+ declare { i8, i32 } @llvm.x86.addcarry.32(i8, i32, i32) #1
; Function Attrs: nounwind readnone
- declare { i8, i64 } @llvm.x86.addcarryx.u64(i8, i64, i64) #1
+ declare { i8, i64 } @llvm.x86.addcarry.64(i8, i64, i64) #1
; Function Attrs: nounwind
declare void @llvm.stackprotector(i8*, i8**) #2
Modified: llvm/trunk/test/CodeGen/X86/adx-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/adx-intrinsics.ll?rev=348737&r1=348736&r2=348737&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/adx-intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/X86/adx-intrinsics.ll Sun Dec 9 22:07:50 2018
@@ -2,26 +2,8 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 --show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=NOADX
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=broadwell --show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=ADX
-declare { i8, i32 } @llvm.x86.addcarryx.u32(i8, i32, i32)
-
-define i8 @test_addcarryx_u32(i8 %c, i32 %a, i32 %b, i8* %ptr) {
-; CHECK-LABEL: test_addcarryx_u32:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; CHECK-NEXT: adcl %edx, %esi ## encoding: [0x11,0xd6]
-; CHECK-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
-; CHECK-NEXT: movl %esi, (%rcx) ## encoding: [0x89,0x31]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %ret = call { i8, i32 } @llvm.x86.addcarryx.u32(i8 %c, i32 %a, i32 %b)
- %1 = extractvalue { i8, i32 } %ret, 1
- %2 = bitcast i8* %ptr to i32*
- store i32 %1, i32* %2, align 1
- %3 = extractvalue { i8, i32 } %ret, 0
- ret i8 %3
-}
-
-define i8 @test_addcarryx_u32_load(i8 %c, i32* %aptr, i32 %b, i8* %ptr) {
-; CHECK-LABEL: test_addcarryx_u32_load:
+define i8 @test_addcarry_32_load(i8 %c, i32* %aptr, i32 %b, i8* %ptr) {
+; CHECK-LABEL: test_addcarry_32_load:
; CHECK: ## %bb.0:
; CHECK-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
; CHECK-NEXT: adcl (%rsi), %edx ## encoding: [0x13,0x16]
@@ -29,7 +11,7 @@ define i8 @test_addcarryx_u32_load(i8 %c
; CHECK-NEXT: movl %edx, (%rcx) ## encoding: [0x89,0x11]
; CHECK-NEXT: retq ## encoding: [0xc3]
%a = load i32, i32* %aptr
- %ret = call { i8, i32 } @llvm.x86.addcarryx.u32(i8 %c, i32 %a, i32 %b)
+ %ret = call { i8, i32 } @llvm.x86.addcarry.32(i8 %c, i32 %a, i32 %b)
%1 = extractvalue { i8, i32 } %ret, 1
%2 = bitcast i8* %ptr to i32*
store i32 %1, i32* %2, align 1
@@ -37,8 +19,8 @@ define i8 @test_addcarryx_u32_load(i8 %c
ret i8 %3
}
-define i8 @test_addcarryx_u32_load2(i8 %c, i32 %a, i32* %bptr, i8* %ptr) {
-; CHECK-LABEL: test_addcarryx_u32_load2:
+define i8 @test_addcarry_32_load2(i8 %c, i32 %a, i32* %bptr, i8* %ptr) {
+; CHECK-LABEL: test_addcarry_32_load2:
; CHECK: ## %bb.0:
; CHECK-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
; CHECK-NEXT: adcl (%rdx), %esi ## encoding: [0x13,0x32]
@@ -46,7 +28,7 @@ define i8 @test_addcarryx_u32_load2(i8 %
; CHECK-NEXT: movl %esi, (%rcx) ## encoding: [0x89,0x31]
; CHECK-NEXT: retq ## encoding: [0xc3]
%b = load i32, i32* %bptr
- %ret = call { i8, i32 } @llvm.x86.addcarryx.u32(i8 %c, i32 %a, i32 %b)
+ %ret = call { i8, i32 } @llvm.x86.addcarry.32(i8 %c, i32 %a, i32 %b)
%1 = extractvalue { i8, i32 } %ret, 1
%2 = bitcast i8* %ptr to i32*
store i32 %1, i32* %2, align 1
@@ -54,35 +36,17 @@ define i8 @test_addcarryx_u32_load2(i8 %
ret i8 %3
}
-declare { i8, i64 } @llvm.x86.addcarryx.u64(i8, i64, i64)
-
-define i8 @test_addcarryx_u64(i8 %c, i64 %a, i64 %b, i8* %ptr) {
-; CHECK-LABEL: test_addcarryx_u64:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; CHECK-NEXT: adcq %rdx, %rsi ## encoding: [0x48,0x11,0xd6]
-; CHECK-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
-; CHECK-NEXT: movq %rsi, (%rcx) ## encoding: [0x48,0x89,0x31]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %ret = call { i8, i64 } @llvm.x86.addcarryx.u64(i8 %c, i64 %a, i64 %b)
- %1 = extractvalue { i8, i64 } %ret, 1
- %2 = bitcast i8* %ptr to i64*
- store i64 %1, i64* %2, align 1
- %3 = extractvalue { i8, i64 } %ret, 0
- ret i8 %3
-}
-
-declare { i8, i32 } @llvm.x86.addcarry.u32(i8, i32, i32)
+declare { i8, i32 } @llvm.x86.addcarry.32(i8, i32, i32)
-define i8 @test_addcarry_u32(i8 %c, i32 %a, i32 %b, i8* %ptr) {
-; CHECK-LABEL: test_addcarry_u32:
+define i8 @test_addcarry_32(i8 %c, i32 %a, i32 %b, i8* %ptr) {
+; CHECK-LABEL: test_addcarry_32:
; CHECK: ## %bb.0:
; CHECK-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
; CHECK-NEXT: adcl %edx, %esi ## encoding: [0x11,0xd6]
; CHECK-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
; CHECK-NEXT: movl %esi, (%rcx) ## encoding: [0x89,0x31]
; CHECK-NEXT: retq ## encoding: [0xc3]
- %ret = call { i8, i32 } @llvm.x86.addcarry.u32(i8 %c, i32 %a, i32 %b)
+ %ret = call { i8, i32 } @llvm.x86.addcarry.32(i8 %c, i32 %a, i32 %b)
%1 = extractvalue { i8, i32 } %ret, 1
%2 = bitcast i8* %ptr to i32*
store i32 %1, i32* %2, align 1
@@ -90,17 +54,17 @@ define i8 @test_addcarry_u32(i8 %c, i32
ret i8 %3
}
-declare { i8, i64 } @llvm.x86.addcarry.u64(i8, i64, i64)
+declare { i8, i64 } @llvm.x86.addcarry.64(i8, i64, i64)
-define i8 @test_addcarry_u64(i8 %c, i64 %a, i64 %b, i8* %ptr) {
-; CHECK-LABEL: test_addcarry_u64:
+define i8 @test_addcarry_64(i8 %c, i64 %a, i64 %b, i8* %ptr) {
+; CHECK-LABEL: test_addcarry_64:
; CHECK: ## %bb.0:
; CHECK-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
; CHECK-NEXT: adcq %rdx, %rsi ## encoding: [0x48,0x11,0xd6]
; CHECK-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
; CHECK-NEXT: movq %rsi, (%rcx) ## encoding: [0x48,0x89,0x31]
; CHECK-NEXT: retq ## encoding: [0xc3]
- %ret = call { i8, i64 } @llvm.x86.addcarry.u64(i8 %c, i64 %a, i64 %b)
+ %ret = call { i8, i64 } @llvm.x86.addcarry.64(i8 %c, i64 %a, i64 %b)
%1 = extractvalue { i8, i64 } %ret, 1
%2 = bitcast i8* %ptr to i64*
store i64 %1, i64* %2, align 1
@@ -108,17 +72,17 @@ define i8 @test_addcarry_u64(i8 %c, i64
ret i8 %3
}
-declare { i8, i32 } @llvm.x86.subborrow.u32(i8, i32, i32)
+declare { i8, i32 } @llvm.x86.subborrow.32(i8, i32, i32)
-define i8 @test_subborrow_u32(i8 %c, i32 %a, i32 %b, i8* %ptr) {
-; CHECK-LABEL: test_subborrow_u32:
+define i8 @test_subborrow_32(i8 %c, i32 %a, i32 %b, i8* %ptr) {
+; CHECK-LABEL: test_subborrow_32:
; CHECK: ## %bb.0:
; CHECK-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
; CHECK-NEXT: sbbl %edx, %esi ## encoding: [0x19,0xd6]
; CHECK-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
; CHECK-NEXT: movl %esi, (%rcx) ## encoding: [0x89,0x31]
; CHECK-NEXT: retq ## encoding: [0xc3]
- %ret = call { i8, i32 } @llvm.x86.subborrow.u32(i8 %c, i32 %a, i32 %b)
+ %ret = call { i8, i32 } @llvm.x86.subborrow.32(i8 %c, i32 %a, i32 %b)
%1 = extractvalue { i8, i32 } %ret, 1
%2 = bitcast i8* %ptr to i32*
store i32 %1, i32* %2, align 1
@@ -126,17 +90,17 @@ define i8 @test_subborrow_u32(i8 %c, i32
ret i8 %3
}
-declare { i8, i64 } @llvm.x86.subborrow.u64(i8, i64, i64)
+declare { i8, i64 } @llvm.x86.subborrow.64(i8, i64, i64)
-define i8 @test_subborrow_u64(i8 %c, i64 %a, i64 %b, i8* %ptr) {
-; CHECK-LABEL: test_subborrow_u64:
+define i8 @test_subborrow_64(i8 %c, i64 %a, i64 %b, i8* %ptr) {
+; CHECK-LABEL: test_subborrow_64:
; CHECK: ## %bb.0:
; CHECK-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
; CHECK-NEXT: sbbq %rdx, %rsi ## encoding: [0x48,0x19,0xd6]
; CHECK-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
; CHECK-NEXT: movq %rsi, (%rcx) ## encoding: [0x48,0x89,0x31]
; CHECK-NEXT: retq ## encoding: [0xc3]
- %ret = call { i8, i64 } @llvm.x86.subborrow.u64(i8 %c, i64 %a, i64 %b)
+ %ret = call { i8, i64 } @llvm.x86.subborrow.64(i8 %c, i64 %a, i64 %b)
%1 = extractvalue { i8, i64 } %ret, 1
%2 = bitcast i8* %ptr to i64*
store i64 %1, i64* %2, align 1
@@ -157,7 +121,7 @@ define i32 @load_crash(i64* nocapture re
%1 = load i64, i64* %a, align 8
%2 = load i64, i64* %b, align 8
%3 = bitcast i64* %res to i8*
- %4 = call { i8, i64 } @llvm.x86.addcarryx.u64(i8 0, i64 %1, i64 %2)
+ %4 = call { i8, i64 } @llvm.x86.addcarry.64(i8 0, i64 %1, i64 %2)
%5 = extractvalue { i8, i64 } %4, 1
%6 = bitcast i8* %3 to i64*
store i64 %5, i64* %6, align 1
@@ -175,7 +139,7 @@ define void @allzeros() {
; CHECK-NEXT: movq %rax, 0 ## encoding: [0x48,0x89,0x04,0x25,0x00,0x00,0x00,0x00]
; CHECK-NEXT: retq ## encoding: [0xc3]
entry:
- %0 = call { i8, i64 } @llvm.x86.addcarryx.u64(i8 0, i64 0, i64 0)
+ %0 = call { i8, i64 } @llvm.x86.addcarry.64(i8 0, i64 0, i64 0)
%1 = extractvalue { i8, i64 } %0, 1
store i64 %1, i64* null, align 1
%2 = extractvalue { i8, i64 } %0, 0
Modified: llvm/trunk/test/CodeGen/X86/stack-folding-adx-x86_64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/stack-folding-adx-x86_64.ll?rev=348737&r1=348736&r2=348737&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/stack-folding-adx-x86_64.ll (original)
+++ llvm/trunk/test/CodeGen/X86/stack-folding-adx-x86_64.ll Sun Dec 9 22:07:50 2018
@@ -13,52 +13,75 @@ define i8 @stack_fold_addcarry_u32(i8 %a
;CHECK-LABEL: stack_fold_addcarry_u32
;CHECK: adcl {{-?[0-9]*}}(%rsp), %{{.*}} {{.*#+}} 4-byte Folded Reload
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
- %2 = tail call i8 @llvm.x86.addcarry.u32(i8 %a0, i32 %a1, i32 %a2, i8* %a3)
- ret i8 %2;
+ %2 = call { i8, i32 } @llvm.x86.addcarry.32(i8 %a0, i32 %a1, i32 %a2)
+ %3 = extractvalue { i8, i32 } %2, 1
+ %4 = bitcast i8* %a3 to i32*
+ store i32 %3, i32* %4, align 1
+ %5 = extractvalue { i8, i32 } %2, 0
+ ret i8 %5
}
-declare i8 @llvm.x86.addcarry.u32(i8, i32, i32, i8*)
define i8 @stack_fold_addcarry_u64(i8 %a0, i64 %a1, i64 %a2, i8* %a3) {
;CHECK-LABEL: stack_fold_addcarry_u64
;CHECK: adcq {{-?[0-9]*}}(%rsp), %{{.*}} {{.*#+}} 8-byte Folded Reload
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
- %2 = tail call i8 @llvm.x86.addcarry.u64(i8 %a0, i64 %a1, i64 %a2, i8* %a3)
- ret i8 %2;
+ %2 = call { i8, i64 } @llvm.x86.addcarry.64(i8 %a0, i64 %a1, i64 %a2)
+ %3 = extractvalue { i8, i64 } %2, 1
+ %4 = bitcast i8* %a3 to i64*
+ store i64 %3, i64* %4, align 1
+ %5 = extractvalue { i8, i64 } %2, 0
+ ret i8 %5
}
-declare i8 @llvm.x86.addcarry.u64(i8, i64, i64, i8*)
define i8 @stack_fold_addcarryx_u32(i8 %a0, i32 %a1, i32 %a2, i8* %a3) {
;CHECK-LABEL: stack_fold_addcarryx_u32
;CHECK: adcl {{-?[0-9]*}}(%rsp), %{{.*}} {{.*#+}} 4-byte Folded Reload
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
- %2 = tail call i8 @llvm.x86.addcarryx.u32(i8 %a0, i32 %a1, i32 %a2, i8* %a3)
- ret i8 %2;
+ %2 = call { i8, i32 } @llvm.x86.addcarry.32(i8 %a0, i32 %a1, i32 %a2)
+ %3 = extractvalue { i8, i32 } %2, 1
+ %4 = bitcast i8* %a3 to i32*
+ store i32 %3, i32* %4, align 1
+ %5 = extractvalue { i8, i32 } %2, 0
+ ret i8 %5
}
-declare i8 @llvm.x86.addcarryx.u32(i8, i32, i32, i8*)
define i8 @stack_fold_addcarryx_u64(i8 %a0, i64 %a1, i64 %a2, i8* %a3) {
;CHECK-LABEL: stack_fold_addcarryx_u64
;CHECK: adcq {{-?[0-9]*}}(%rsp), %{{.*}} {{.*#+}} 8-byte Folded Reload
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
- %2 = tail call i8 @llvm.x86.addcarryx.u64(i8 %a0, i64 %a1, i64 %a2, i8* %a3)
- ret i8 %2;
+ %2 = call { i8, i64 } @llvm.x86.addcarry.64(i8 %a0, i64 %a1, i64 %a2)
+ %3 = extractvalue { i8, i64 } %2, 1
+ %4 = bitcast i8* %a3 to i64*
+ store i64 %3, i64* %4, align 1
+ %5 = extractvalue { i8, i64 } %2, 0
+ ret i8 %5
}
-declare i8 @llvm.x86.addcarryx.u64(i8, i64, i64, i8*)
define i8 @stack_fold_subborrow_u32(i8 %a0, i32 %a1, i32 %a2, i8* %a3) {
;CHECK-LABEL: stack_fold_subborrow_u32
;CHECK: sbbl {{-?[0-9]*}}(%rsp), %{{.*}} {{.*#+}} 4-byte Folded Reload
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
- %2 = tail call i8 @llvm.x86.subborrow.u32(i8 %a0, i32 %a1, i32 %a2, i8* %a3)
- ret i8 %2;
+ %2 = call { i8, i32 } @llvm.x86.subborrow.32(i8 %a0, i32 %a1, i32 %a2)
+ %3 = extractvalue { i8, i32 } %2, 1
+ %4 = bitcast i8* %a3 to i32*
+ store i32 %3, i32* %4, align 1
+ %5 = extractvalue { i8, i32 } %2, 0
+ ret i8 %5
}
-declare i8 @llvm.x86.subborrow.u32(i8, i32, i32, i8*)
define i8 @stack_fold_subborrow_u64(i8 %a0, i64 %a1, i64 %a2, i8* %a3) {
;CHECK-LABEL: stack_fold_subborrow_u64
;CHECK: sbbq {{-?[0-9]*}}(%rsp), %{{.*}} {{.*#+}} 8-byte Folded Reload
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
- %2 = tail call i8 @llvm.x86.subborrow.u64(i8 %a0, i64 %a1, i64 %a2, i8* %a3)
- ret i8 %2;
+ %2 = call { i8, i64 } @llvm.x86.subborrow.64(i8 %a0, i64 %a1, i64 %a2)
+ %3 = extractvalue { i8, i64 } %2, 1
+ %4 = bitcast i8* %a3 to i64*
+ store i64 %3, i64* %4, align 1
+ %5 = extractvalue { i8, i64 } %2, 0
+ ret i8 %5
}
-declare i8 @llvm.x86.subborrow.u64(i8, i64, i64, i8*)
+
+declare { i8, i32 } @llvm.x86.addcarry.32(i8, i32, i32)
+declare { i8, i64 } @llvm.x86.addcarry.64(i8, i64, i64)
+declare { i8, i32 } @llvm.x86.subborrow.32(i8, i32, i32)
+declare { i8, i64 } @llvm.x86.subborrow.64(i8, i64, i64)
Modified: llvm/trunk/test/CodeGen/X86/stack-folding-adx.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/stack-folding-adx.mir?rev=348737&r1=348736&r2=348737&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/stack-folding-adx.mir (original)
+++ llvm/trunk/test/CodeGen/X86/stack-folding-adx.mir Sun Dec 9 22:07:50 2018
@@ -5,7 +5,7 @@
; Function Attrs: nounwind
define i8 @stack_fold_adcx32(i8 %a0, i32 %a1, i32 %a2, i8* %a3) #0 {
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
- %2 = call { i8, i32 } @llvm.x86.addcarryx.u32(i8 %a0, i32 %a1, i32 %a2)
+ %2 = call { i8, i32 } @llvm.x86.addcarry.32(i8 %a0, i32 %a1, i32 %a2)
%3 = extractvalue { i8, i32 } %2, 1
%4 = bitcast i8* %a3 to i32*
store i32 %3, i32* %4, align 1
@@ -16,7 +16,7 @@
; Function Attrs: nounwind
define i8 @stack_fold_adcx64(i8 %a0, i64 %a1, i64 %a2, i8* %a3) #0 {
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
- %2 = call { i8, i64 } @llvm.x86.addcarryx.u64(i8 %a0, i64 %a1, i64 %a2)
+ %2 = call { i8, i64 } @llvm.x86.addcarry.64(i8 %a0, i64 %a1, i64 %a2)
%3 = extractvalue { i8, i64 } %2, 1
%4 = bitcast i8* %a3 to i64*
store i64 %3, i64* %4, align 1
@@ -26,7 +26,7 @@
define i8 @stack_fold_adox32(i8 %a0, i32 %a1, i32 %a2, i8* %a3) #0 {
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
- %2 = call { i8, i32 } @llvm.x86.addcarryx.u32(i8 %a0, i32 %a1, i32 %a2)
+ %2 = call { i8, i32 } @llvm.x86.addcarry.32(i8 %a0, i32 %a1, i32 %a2)
%3 = extractvalue { i8, i32 } %2, 1
%4 = bitcast i8* %a3 to i32*
store i32 %3, i32* %4, align 1
@@ -37,7 +37,7 @@
; Function Attrs: nounwind
define i8 @stack_fold_adox64(i8 %a0, i64 %a1, i64 %a2, i8* %a3) #0 {
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
- %2 = call { i8, i64 } @llvm.x86.addcarryx.u64(i8 %a0, i64 %a1, i64 %a2)
+ %2 = call { i8, i64 } @llvm.x86.addcarry.64(i8 %a0, i64 %a1, i64 %a2)
%3 = extractvalue { i8, i64 } %2, 1
%4 = bitcast i8* %a3 to i64*
store i64 %3, i64* %4, align 1
@@ -46,10 +46,10 @@
}
; Function Attrs: nounwind readnone
- declare { i8, i32 } @llvm.x86.addcarryx.u32(i8, i32, i32) #1
+ declare { i8, i32 } @llvm.x86.addcarry.32(i8, i32, i32) #1
; Function Attrs: nounwind readnone
- declare { i8, i64 } @llvm.x86.addcarryx.u64(i8, i64, i64) #1
+ declare { i8, i64 } @llvm.x86.addcarry.64(i8, i64, i64) #1
; Function Attrs: nounwind
declare void @llvm.stackprotector(i8*, i8**) #2
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