[PATCH] D55474: [AMDGPU] Extend constant folding for logical operations

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir:209-211
+    %1 = S_LOAD_DWORDX2_IMM %0, 36, 0
+    %2 = COPY %1.sub1
+    %3 = COPY %1.sub0
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Somehow this MIR looks ancient. The virtual registers should have the class annotations and then you can drop the register section. You can use -run-pass=none to convert this (and after delete the frame info etc.)


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D55474/new/

https://reviews.llvm.org/D55474