[PATCH] D55402: [AMDGPU] Simplify negated condition

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp:140
+
+  auto *And = TRI->findReachingDef(CondReg, AMDGPU::NoSubRegister,
+                                   *I, MRI, LIS);
----------------
rampitec wrote:
> nhaehnle wrote:
> > Does this (and the other findReachingDef) need to be guarded to ensure the instructions come from the same basic block?
> > 
> > Or, to be more precise, against changes to EXEC in between?
> findReachingDef does that check. Instructions must belong to the same BB. Otherwise a dominator tree would be required. Specific check for exec is not needed, none of the instructions in that chain modify exec, and there can be no such instruction in between of first two as they are not terminators.
The dominator tree is implicitly used by LiveIntervals anyway


================
Comment at: test/CodeGen/AMDGPU/optimize-negated-cond.ll:10
+; GCN:   s_cbranch_vccz BB0_4
+define amdgpu_kernel void @test(float addrspace(1)* %arg1) {
+bb:
----------------
rampitec wrote:
> arsenm wrote:
> > Can this be reduced?
> It is already reduced with bug point. In presence of mir test I can drop it altogether if you want.
Now that you have the specific pattern, you should be able to shrink it?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D55402/new/

https://reviews.llvm.org/D55402