[PATCH] D55448: [DAGCombiner] allow hoisting vector bitwise logic ahead of truncates

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: kparzysz, craig.topper, RKSimon.
Herald added subscribers: kristof.beyls, javed.absar, mcrosier.

The transform performs a bitwise logic op in a wider type followed by truncate when both inputs are truncated from the same source type:
logic_op (truncate x), (truncate y) --> truncate (logic_op x, y)

There are a bunch of other checks that should prevent doing this when it might be harmful.

We already do this for scalars. The vector limitation was shared with a check for the case when the operands are extended. I'm not sure if that limit is needed either, but that would be a separate patch.


https://reviews.llvm.org/D55448

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/ARM/setcc-logic.ll
  test/CodeGen/Hexagon/autohvx/bitwise-pred-128b.ll
  test/CodeGen/Hexagon/autohvx/bitwise-pred-64b.ll
  test/CodeGen/X86/avx512-select.ll
  test/CodeGen/X86/bitcast-and-setcc-128.ll
  test/CodeGen/X86/bitcast-and-setcc-256.ll
  test/CodeGen/X86/bitcast-and-setcc-512.ll
  test/CodeGen/X86/psubus.ll
  test/CodeGen/X86/vector-rotate-128.ll
  test/CodeGen/X86/vector-rotate-256.ll
  test/CodeGen/X86/vector-rotate-512.ll

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