[PATCH] D50496: [RISCV] Implment pseudo instructions for load/store from a symbol address.

[James Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


================
Comment at: lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:1341
+  MCOperand TmpReg = Inst.getOperand(1);
+  const MCExpr *Symbol = Inst.getOperand(2).getExpr();
+
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Further investigation reveals that, for GNU as, the symbol is still `Operands[1]`, and the temporary register is `Operands[2]`, i.e. `sw a0, foo, t0`.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D50496/new/

https://reviews.llvm.org/D50496