[PATCH] D55375: [AArch64] Refactor the scheduling predicates

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64SchedPredicates.td:17-27
+// Check the extension type in arithmetic instructions.
+let FunctionMapper = "AArch64_AM::getArithExtendType" in {
+  def CheckExtUXTB                      : CheckImmOperand_s<3, "AArch64_AM::UXTB">;
+  def CheckExtUXTH                      : CheckImmOperand_s<3, "AArch64_AM::UXTH">;
+  def CheckExtUXTW                      : CheckImmOperand_s<3, "AArch64_AM::UXTW">;
+  def CheckExtUXTX                      : CheckImmOperand_s<3, "AArch64_AM::UXTX">;
+  def CheckExtSXTB                      : CheckImmOperand_s<3, "AArch64_AM::SXTB">;
----------------
Needed by D55345 too.
Without that definition, patch D55345 will not build because CheckExtUXTW is not defined (see AArch64SchedPredExynos.td:29).


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Comment at: llvm/lib/Target/AArch64/AArch64SchedPredicates.td:29-33
+// Check for shifting in extended arithmetic instructions.
+foreach I = {0-3} in {
+  let FunctionMapper = "AArch64_AM::getArithShiftValue" in
+  def CheckExtBy#I                      : CheckImmOperand<3, I>;
+}
----------------
This is needed by D55345 too.


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Comment at: llvm/lib/Target/AArch64/AArch64SchedPredicates.td:64-65
 
+// Identify whether an instruction is the 64-bit NEON form based on its result.
+def CheckDForm             : CheckAll<[CheckIsRegOperand<0>,
+                                       CheckAny<[CheckRegOperand<0, D0>,
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Needed by D55345.


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Comment at: llvm/lib/Target/AArch64/AArch64SchedPredicates.td:100
+// Identify whether an instruction is the 128-bit NEON form based on its result.
+def CheckQForm             : CheckAll<[CheckIsRegOperand<0>,
+                                       CheckAny<[CheckRegOperand<0, Q0>,
----------------
Same.


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Comment at: llvm/lib/Target/AArch64/AArch64SchedPredicates.td:135
 // Identify arithmetic instructions with extend.
-def IsArithExtPred        : CheckOpcode<[ADDWrx, ADDXrx, ADDXrx64, ADDSWrx, ADDSXrx, ADDSXrx64,
-                                         SUBWrx, SUBXrx, SUBXrx64, SUBSWrx, SUBSXrx, SUBSXrx64]>;
+def IsArithExt32Op         : CheckOpcode<[ADDWrx, ADDXrx, ADDSWrx, ADDSXrx,
+                                          SUBWrx, SUBXrx, SUBSWrx, SUBSXrx]>;
----------------
This definition is also needed by your other patch D55345 in AArch64SchedPredExynos.td:25


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Comment at: llvm/lib/Target/AArch64/AArch64SchedPredicates.td:137
+                                          SUBWrx, SUBXrx, SUBSWrx, SUBSXrx]>;
+def IsArithExt64Op         : CheckOpcode<[ADDXrx64, ADDSXrx64,
+                                          SUBXrx64, SUBSXrx64]>;
----------------
Same.
It is required by D55345 in AArch64SchedPredExynos.td:35


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D55375/new/

https://reviews.llvm.org/D55375