[PATCH] D54143: [WIP, RISCV] Generate address sequences suitable for mcmodel=medium

James Clarke via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Dec 6 05:28:55 PST 2018


jrtc27 added a comment.

In D54143#1321182 <https://reviews.llvm.org/D54143#1321182>, @rogfer01 wrote:

> > My only problem with that approach is that it seems wrong to expand PseudoLLA the same way I am expanding PseudoAddrPCRel, IE allowing the AUIPC operand to be decided by codegen.
>
> I'm not sure to follow here.
>
> I think @jrtc27 means that, instead of adding a new `PseudoAddrPCRel` and select it from a `WrapperPCRel`, we could select `PseudoLLA` and then expand it in `RISCVExpandPseudoInsts`.
>
> That said, I presume at some point we will want to add codegen for GOT-addressing. We have a few options here but if we reuse the `WrapperPCRel` and we use a different target flag to record that this is a GOT-relocation, then the expansion of `PseudoLLA` in the codegen flow and the asm parser flow will be different (the latter always doing `%pcrel_hi` while the former might be able to do both `%pcrel_hi` / `%got_pcrel_hi`). This does not seem ideal to me. Adding another target-specific DAG (e.g. `WrapperGOTRel`) node is workable but feels unnecessary.


But we wouldn't be using `PseudoLLA`, we'd be using `PseudoLA` for things that aren't assumed DSO-local. The CodeGen expansion for both would be identical to the AsmParser (well, except that currently CodeGen is operating on MBBs, but it's equivalent).


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