[PATCH] D55341: [RISCV, WIP] Support assembling TLS add and associated modifiers
Lewis Revill via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 5 14:09:50 PST 2018
lewis-revill created this revision.
lewis-revill added reviewers: asb, rogfer01, jrtc27.
Herald added subscribers: llvm-commits, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, mgrang, edward-jones, zzheng, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar.
This patch adds support in the MC layer for parsing and assembling the 4-operand add instruction needed for TLS addressing. This also involves parsing the %tprel_hi, %tprel_lo and %tprel_add operand modifiers.
Repository:
rL LLVM
https://reviews.llvm.org/D55341
Files:
lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h
lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h
lib/Target/RISCV/RISCVInstrInfo.td
test/MC/RISCV/rv32d-invalid.s
test/MC/RISCV/rv32f-invalid.s
test/MC/RISCV/rv32i-invalid.s
test/MC/RISCV/rv32i-valid.s
test/MC/RISCV/rv64i-invalid.s
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