[llvm] r348298 - [PowerPC] Make no-PIC default to match GCC - LLVM
Stefan Pintilie via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 4 12:14:57 PST 2018
Author: stefanp
Date: Tue Dec 4 12:14:57 2018
New Revision: 348298
URL: http://llvm.org/viewvc/llvm-project?rev=348298&view=rev
Log:
[PowerPC] Make no-PIC default to match GCC - LLVM
Change the default for PowerPC LE to -fno-PIC.
Differential Revision: https://reviews.llvm.org/D53383
Modified:
llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
llvm/trunk/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll
llvm/trunk/test/CodeGen/PowerPC/addegluecrash.ll
llvm/trunk/test/CodeGen/PowerPC/atomics-constant.ll
llvm/trunk/test/CodeGen/PowerPC/f128-aggregates.ll
llvm/trunk/test/CodeGen/PowerPC/f128-conv.ll
llvm/trunk/test/CodeGen/PowerPC/f128-truncateNconv.ll
llvm/trunk/test/CodeGen/PowerPC/f128-vecExtractNconv.ll
llvm/trunk/test/CodeGen/PowerPC/fast-isel-call.ll
llvm/trunk/test/CodeGen/PowerPC/mcm-13.ll
llvm/trunk/test/CodeGen/PowerPC/mcm-6.ll
llvm/trunk/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
llvm/trunk/test/CodeGen/PowerPC/ppc64-blnop.ll
llvm/trunk/test/CodeGen/PowerPC/ppc64-i128-abi.ll
llvm/trunk/test/CodeGen/PowerPC/ppc64le-aggregates.ll
llvm/trunk/test/CodeGen/PowerPC/ppcf128-endian.ll
llvm/trunk/test/CodeGen/PowerPC/pr32140.ll
llvm/trunk/test/CodeGen/PowerPC/preemption.ll
llvm/trunk/test/CodeGen/PowerPC/save-bp.ll
llvm/trunk/test/CodeGen/PowerPC/sjlj_no0x.ll
llvm/trunk/test/CodeGen/PowerPC/swaps-le-6.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesi32gtu.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesi32ltu.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesieqsc.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesieqsi.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesieqsll.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesieqss.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesiequc.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesiequi.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesiequll.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesiequs.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesigesc.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesigesi.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesigesll.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesigess.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesigtsc.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesigtsi.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesigtsll.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesigtss.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesigtuc.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesigtui.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesigtus.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesilesc.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesilesi.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesilesll.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesiless.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesinesc.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesinesi.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesinesll.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesiness.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesineuc.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesineui.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesineull.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesineus.ll
llvm/trunk/test/CodeGen/PowerPC/testCompareslleqsc.ll
llvm/trunk/test/CodeGen/PowerPC/testCompareslleqsi.ll
llvm/trunk/test/CodeGen/PowerPC/testCompareslleqsll.ll
llvm/trunk/test/CodeGen/PowerPC/testCompareslleqss.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllequc.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllequi.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllequll.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllequs.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllgesc.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllgesi.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllgesll.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllgess.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllgtsll.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllgtuc.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllgtui.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllgtus.ll
llvm/trunk/test/CodeGen/PowerPC/testCompareslllesc.ll
llvm/trunk/test/CodeGen/PowerPC/testCompareslllesi.ll
llvm/trunk/test/CodeGen/PowerPC/testCompareslllesll.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllless.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllltui.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllnesll.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllneull.ll
llvm/trunk/test/CodeGen/PowerPC/toc-float.ll
llvm/trunk/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll
llvm/trunk/test/CodeGen/PowerPC/xray-tail-call-sled.ll
Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Tue Dec 4 12:14:57 2018
@@ -214,11 +214,11 @@ static Reloc::Model getEffectiveRelocMod
if (TT.isOSDarwin())
return Reloc::DynamicNoPIC;
- // Non-darwin 64-bit platforms are PIC by default.
- if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le)
+ // Big Endian PPC is PIC by default.
+ if (TT.getArch() == Triple::ppc64)
return Reloc::PIC_;
- // 32-bit is static by default.
+ // Rest are static by default.
return Reloc::Static;
}
Modified: llvm/trunk/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll Tue Dec 4 12:14:57 2018
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
; The instructions addis,addi, bl are used to calculate the address of TLS
; thread local variables. These TLS access code sequences are generated
; repeatedly every time the thread local variable is accessed. By communicating
Modified: llvm/trunk/test/CodeGen/PowerPC/addegluecrash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/addegluecrash.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/addegluecrash.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/addegluecrash.ll Tue Dec 4 12:14:57 2018
@@ -27,6 +27,7 @@ define void @bn_mul_comba8(i64* nocaptur
; CHECK-NEXT: mr 4, 10
; CHECK-NEXT: clrldi 4, 4, 32
; CHECK-NEXT: std 4, 0(3)
+; CHECK-NEXT: std 6, -8(1) # 8-byte Folded Spill
; CHECK-NEXT: blr
%1 = load i64, i64* %a, align 8
%conv = zext i64 %1 to i128
Modified: llvm/trunk/test/CodeGen/PowerPC/atomics-constant.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/atomics-constant.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/atomics-constant.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/atomics-constant.ll Tue Dec 4 12:14:57 2018
@@ -8,14 +8,14 @@ target triple = "powerpc64le-unknown-lin
define i64 @foo() {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis 3, 2, .LC0 at toc@ha
+; CHECK-NEXT: addis 3, 2, a at toc@ha
; CHECK-NEXT: li 4, 0
-; CHECK-NEXT: ld 3, .LC0 at toc@l(3)
+; CHECK-NEXT: addi 3, 3, a at toc@l
; CHECK-NEXT: cmpd 7, 4, 4
; CHECK-NEXT: ld 3, 0(3)
+; CHECK-NEXT: li 3, 0
; CHECK-NEXT: bne- 7, .+4
; CHECK-NEXT: isync
-; CHECK-NEXT: li 3, 0
; CHECK-NEXT: blr
entry:
%value = load atomic i64, i64* @a acquire, align 8
Modified: llvm/trunk/test/CodeGen/PowerPC/f128-aggregates.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/f128-aggregates.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/f128-aggregates.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/f128-aggregates.ll Tue Dec 4 12:14:57 2018
@@ -1,7 +1,7 @@
-; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
+; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
; RUN: -enable-ppc-quad-precision -verify-machineinstrs \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
-; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown \
+; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown \
; RUN: -enable-ppc-quad-precision -verify-machineinstrs \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \
; RUN: | FileCheck -check-prefix=CHECK-BE %s
Modified: llvm/trunk/test/CodeGen/PowerPC/f128-conv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/f128-conv.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/f128-conv.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/f128-conv.ll Tue Dec 4 12:14:57 2018
@@ -1,4 +1,4 @@
-; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
+; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
; RUN: -enable-ppc-quad-precision -ppc-vsr-nums-as-vr \
; RUN: -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s
Modified: llvm/trunk/test/CodeGen/PowerPC/f128-truncateNconv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/f128-truncateNconv.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/f128-truncateNconv.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/f128-truncateNconv.ll Tue Dec 4 12:14:57 2018
@@ -1,4 +1,4 @@
-; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
+; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
; RUN: -verify-machineinstrs -enable-ppc-quad-precision \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
Modified: llvm/trunk/test/CodeGen/PowerPC/f128-vecExtractNconv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/f128-vecExtractNconv.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/f128-vecExtractNconv.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/f128-vecExtractNconv.ll Tue Dec 4 12:14:57 2018
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -ppc-vsr-nums-as-vr \
-; RUN: -ppc-asm-full-reg-names -verify-machineinstrs \
+; RUN: -relocation-model=pic -ppc-asm-full-reg-names -verify-machineinstrs \
; RUN: -enable-ppc-quad-precision < %s | FileCheck %s
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown -ppc-vsr-nums-as-vr \
; RUN: -ppc-asm-full-reg-names -verify-machineinstrs \
Modified: llvm/trunk/test/CodeGen/PowerPC/fast-isel-call.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/fast-isel-call.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/fast-isel-call.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/fast-isel-call.ll Tue Dec 4 12:14:57 2018
@@ -2,7 +2,7 @@
; registers and with -fast-isel-abort=1 turned on the test case will then fail.
; When fastisel better supports VSX fix up this test case.
;
-; RUN: llc < %s -O0 -verify-machineinstrs -mattr=-vsx -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -ppc-late-peephole=true | FileCheck %s --check-prefix=ELF64
+; RUN: llc < %s -O0 -relocation-model=pic -verify-machineinstrs -mattr=-vsx -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -ppc-late-peephole=true | FileCheck %s --check-prefix=ELF64
define i32 @t1(i8 signext %a) nounwind {
%1 = sext i8 %a to i32
Modified: llvm/trunk/test/CodeGen/PowerPC/mcm-13.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/mcm-13.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/mcm-13.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/mcm-13.ll Tue Dec 4 12:14:57 2018
@@ -1,5 +1,5 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck %s
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck %s
; Test correct code generation for medium and large code model
; for loading and storing a weak variable
Modified: llvm/trunk/test/CodeGen/PowerPC/mcm-6.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/mcm-6.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/mcm-6.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/mcm-6.ll Tue Dec 4 12:14:57 2018
@@ -1,5 +1,5 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large < %s | FileCheck %s
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium < %s | FileCheck %s
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large < %s | FileCheck %s
; Test correct code generation for medium and large code model
; for loading and storing a tentatively defined variable.
Modified: llvm/trunk/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll Tue Dec 4 12:14:57 2018
@@ -1,8 +1,8 @@
; RUN: llc < %s -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-linux-gnu \
-; RUN: -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr8 \
+; RUN: -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr8 -relocation-model=pic \
; RUN: | FileCheck %s
; RUN: llc < %s -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-linux-gnu \
-; RUN: -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr8 \
+; RUN: -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr8 -relocation-model=pic \
; RUN: | FileCheck %s -check-prefix=CHECK-LE
; The build[csilf] functions simply test the scalar_to_vector handling with
Modified: llvm/trunk/test/CodeGen/PowerPC/ppc64-blnop.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/ppc64-blnop.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/ppc64-blnop.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/ppc64-blnop.ll Tue Dec 4 12:14:57 2018
@@ -1,11 +1,11 @@
-; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s
-; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s
-; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s
; RUN: llc < %s -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s
-; RUN: llc < %s -function-sections -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK-FS
+; RUN: llc < %s -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s
+; RUN: llc < %s -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s
+; RUN: llc < %s -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s
+; RUN: llc < %s -relocation-model=pic -function-sections -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK-FS
; RUN: llc < %s -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s
-; RUN: llc < %s -function-sections -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK-FS
-; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: llc < %s -relocation-model=pic -function-sections -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK-FS
+; RUN: llc < %s -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -code-model=small -mcpu=pwr8 | FileCheck %s -check-prefix=SCM
%class.T = type { [2 x i8] }
Modified: llvm/trunk/test/CodeGen/PowerPC/ppc64-i128-abi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/ppc64-i128-abi.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/ppc64-i128-abi.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/ppc64-i128-abi.ll Tue Dec 4 12:14:57 2018
@@ -1,33 +1,33 @@
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 < %s | FileCheck %s -check-prefix=CHECK-LE \
; RUN: --implicit-check-not xxswapd
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr8 < %s | FileCheck %s -check-prefix=CHECK-BE
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX \
; RUN: --implicit-check-not xxswapd
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-BE-NOVSX
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -mattr=-vsx < %s | \
; RUN: FileCheck %s -check-prefix=CHECK-LE-NOVSX --implicit-check-not xxswapd
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s -check-prefix=CHECK-P9 --implicit-check-not xxswapd
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX \
; RUN: --implicit-check-not xxswapd
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -mattr=-power9-vector -mattr=-direct-move < %s | \
; RUN: FileCheck %s -check-prefix=CHECK-LE --implicit-check-not xxswapd
Modified: llvm/trunk/test/CodeGen/PowerPC/ppc64le-aggregates.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/ppc64le-aggregates.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/ppc64le-aggregates.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/ppc64le-aggregates.ll Tue Dec 4 12:14:57 2018
@@ -1,8 +1,8 @@
-; RUN: llc -verify-machineinstrs < %s -mcpu=pwr8 \
+; RUN: llc -relocation-model=pic -verify-machineinstrs < %s -mcpu=pwr8 \
; RUN: -mattr=+altivec -mattr=-vsx | FileCheck %s
-; RUN: llc -verify-machineinstrs < %s -mattr=+altivec \
+; RUN: llc -relocation-model=pic -verify-machineinstrs < %s -mattr=+altivec \
; RUN: -mattr=-vsx | FileCheck %s
-; RUN: llc -verify-machineinstrs < %s -mcpu=pwr9 \
+; RUN: llc -relocation-model=pic -verify-machineinstrs < %s -mcpu=pwr9 \
; RUN: -mattr=-direct-move -mattr=+altivec | FileCheck %s
; Currently VSX support is disabled for this test because we generate lxsdx
Modified: llvm/trunk/test/CodeGen/PowerPC/ppcf128-endian.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/ppcf128-endian.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/ppcf128-endian.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/ppcf128-endian.ll Tue Dec 4 12:14:57 2018
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec -mattr=-vsx < %s | FileCheck %s
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec -mattr=-vsx < %s | FileCheck %s
target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu"
Modified: llvm/trunk/test/CodeGen/PowerPC/pr32140.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/pr32140.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/pr32140.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/pr32140.ll Tue Dec 4 12:14:57 2018
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=powerpc64le-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
-; RUN: llc -mtriple=powerpc64-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64le-linux-gnu -mcpu=pwr8 < %s | FileCheck %s --check-prefix CHECK-LE
+; RUN: llc -mtriple=powerpc64-linux-gnu -mcpu=pwr8 < %s | FileCheck %s --check-prefix CHECK-BE
@as = common local_unnamed_addr global i16 0, align 2
@bs = common local_unnamed_addr global i16 0, align 2
@@ -10,10 +10,33 @@
define void @bswapStorei64Toi32() {
; CHECK-LABEL: bswapStorei64Toi32:
; CHECK: # %bb.0: # %entry
-; CHECK: lwa 3, 0(3)
+; CHECK-NEXT: addis 3, 2, ai at toc@ha
+; CHECK-NEXT: addis 4, 2, bi at toc@ha
+; CHECK-NEXT: lwa 3, ai at toc@l(3)
+; CHECK-NEXT: addi 4, 4, bi at toc@l
; CHECK-NEXT: rldicl 3, 3, 32, 32
; CHECK-NEXT: stwbrx 3, 0, 4
; CHECK-NEXT: blr
+; CHECK-LE-LABEL: bswapStorei64Toi32:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: addis 3, 2, ai at toc@ha
+; CHECK-LE-NEXT: addis 4, 2, bi at toc@ha
+; CHECK-LE-NEXT: lwa 3, ai at toc@l(3)
+; CHECK-LE-NEXT: addi 4, 4, bi at toc@l
+; CHECK-LE-NEXT: rldicl 3, 3, 32, 32
+; CHECK-LE-NEXT: stwbrx 3, 0, 4
+; CHECK-LE-NEXT: blr
+;
+; CHECK-BE-LABEL: bswapStorei64Toi32:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis 3, 2, .LC0 at toc@ha
+; CHECK-BE-NEXT: addis 4, 2, .LC1 at toc@ha
+; CHECK-BE-NEXT: ld 3, .LC0 at toc@l(3)
+; CHECK-BE-NEXT: ld 4, .LC1 at toc@l(4)
+; CHECK-BE-NEXT: lwa 3, 0(3)
+; CHECK-BE-NEXT: rldicl 3, 3, 32, 32
+; CHECK-BE-NEXT: stwbrx 3, 0, 4
+; CHECK-BE-NEXT: blr
entry:
%0 = load i32, i32* @ai, align 4
%conv.i = sext i32 %0 to i64
@@ -26,10 +49,33 @@ entry:
define void @bswapStorei32Toi16() {
; CHECK-LABEL: bswapStorei32Toi16:
; CHECK: # %bb.0: # %entry
-; CHECK: lha 3, 0(3)
+; CHECK-NEXT: addis 3, 2, as at toc@ha
+; CHECK-NEXT: addis 4, 2, bs at toc@ha
+; CHECK-NEXT: lha 3, as at toc@l(3)
+; CHECK-NEXT: addi 4, 4, bs at toc@l
; CHECK-NEXT: srwi 3, 3, 16
; CHECK-NEXT: sthbrx 3, 0, 4
; CHECK-NEXT: blr
+; CHECK-LE-LABEL: bswapStorei32Toi16:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: addis 3, 2, as at toc@ha
+; CHECK-LE-NEXT: addis 4, 2, bs at toc@ha
+; CHECK-LE-NEXT: lha 3, as at toc@l(3)
+; CHECK-LE-NEXT: addi 4, 4, bs at toc@l
+; CHECK-LE-NEXT: srwi 3, 3, 16
+; CHECK-LE-NEXT: sthbrx 3, 0, 4
+; CHECK-LE-NEXT: blr
+;
+; CHECK-BE-LABEL: bswapStorei32Toi16:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis 3, 2, .LC2 at toc@ha
+; CHECK-BE-NEXT: addis 4, 2, .LC3 at toc@ha
+; CHECK-BE-NEXT: ld 3, .LC2 at toc@l(3)
+; CHECK-BE-NEXT: ld 4, .LC3 at toc@l(4)
+; CHECK-BE-NEXT: lha 3, 0(3)
+; CHECK-BE-NEXT: srwi 3, 3, 16
+; CHECK-BE-NEXT: sthbrx 3, 0, 4
+; CHECK-BE-NEXT: blr
entry:
%0 = load i16, i16* @as, align 2
%conv.i = sext i16 %0 to i32
@@ -42,10 +88,33 @@ entry:
define void @bswapStorei64Toi16() {
; CHECK-LABEL: bswapStorei64Toi16:
; CHECK: # %bb.0: # %entry
-; CHECK: lha 3, 0(3)
+; CHECK-NEXT: addis 3, 2, as at toc@ha
+; CHECK-NEXT: addis 4, 2, bs at toc@ha
+; CHECK-NEXT: lha 3, as at toc@l(3)
+; CHECK-NEXT: addi 4, 4, bs at toc@l
; CHECK-NEXT: rldicl 3, 3, 16, 48
; CHECK-NEXT: sthbrx 3, 0, 4
; CHECK-NEXT: blr
+; CHECK-LE-LABEL: bswapStorei64Toi16:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: addis 3, 2, as at toc@ha
+; CHECK-LE-NEXT: addis 4, 2, bs at toc@ha
+; CHECK-LE-NEXT: lha 3, as at toc@l(3)
+; CHECK-LE-NEXT: addi 4, 4, bs at toc@l
+; CHECK-LE-NEXT: rldicl 3, 3, 16, 48
+; CHECK-LE-NEXT: sthbrx 3, 0, 4
+; CHECK-LE-NEXT: blr
+;
+; CHECK-BE-LABEL: bswapStorei64Toi16:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis 3, 2, .LC2 at toc@ha
+; CHECK-BE-NEXT: addis 4, 2, .LC3 at toc@ha
+; CHECK-BE-NEXT: ld 3, .LC2 at toc@l(3)
+; CHECK-BE-NEXT: ld 4, .LC3 at toc@l(4)
+; CHECK-BE-NEXT: lha 3, 0(3)
+; CHECK-BE-NEXT: rldicl 3, 3, 16, 48
+; CHECK-BE-NEXT: sthbrx 3, 0, 4
+; CHECK-BE-NEXT: blr
entry:
%0 = load i16, i16* @as, align 2
%conv.i = sext i16 %0 to i64
Modified: llvm/trunk/test/CodeGen/PowerPC/preemption.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/preemption.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/preemption.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/preemption.ll Tue Dec 4 12:14:57 2018
@@ -1,4 +1,5 @@
-; RUN: llc -mtriple powerpc64le-unkown-gnu-linux < %s | FileCheck %s
+; RUN: llc -mtriple powerpc64le-unkown-gnu-linux -relocation-model=pic \
+; RUN: < %s | FileCheck %s
; RUN: llc -mtriple powerpc64le-unkown-gnu-linux -relocation-model=static \
; RUN: < %s | FileCheck --check-prefix=STATIC %s
; RUN: llc -mtriple powerpc64le-unkown-gnu-linux -relocation-model=pic \
Modified: llvm/trunk/test/CodeGen/PowerPC/save-bp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/save-bp.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/save-bp.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/save-bp.ll Tue Dec 4 12:14:57 2018
@@ -1,6 +1,6 @@
; RUN: llc -mtriple=ppc64-- -ppc-always-use-base-pointer < %s | FileCheck %s --check-prefix CHECK --check-prefix PPC64
-; RUN: llc -ppc-always-use-base-pointer < %s | FileCheck %s --check-prefix CHECK --check-prefix PPC32
-; RUN: llc -ppc-always-use-base-pointer -relocation-model pic < %s | FileCheck %s --check-prefix CHECK --check-prefix PPC32PIC
+; RUN: llc -ppc-always-use-base-pointer -relocation-model=static < %s | FileCheck %s --check-prefix CHECK --check-prefix PPC32
+; RUN: llc -ppc-always-use-base-pointer -relocation-model=pic < %s | FileCheck %s --check-prefix CHECK --check-prefix PPC32PIC
; CHECK-LABEL: fred:
Modified: llvm/trunk/test/CodeGen/PowerPC/sjlj_no0x.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/sjlj_no0x.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/sjlj_no0x.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/sjlj_no0x.ll Tue Dec 4 12:14:57 2018
@@ -1,6 +1,6 @@
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -relocation-model=pic -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -relocation-model=pic -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -relocation-model=pic -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -verify-machineinstrs | FileCheck %s
target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu"
Modified: llvm/trunk/test/CodeGen/PowerPC/swaps-le-6.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/swaps-le-6.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/swaps-le-6.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/swaps-le-6.ll Tue Dec 4 12:14:57 2018
@@ -1,13 +1,13 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-vsr-nums-as-vr \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr8 -ppc-vsr-nums-as-vr \
; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -O3 < %s | FileCheck %s
-; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \
+; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \
; RUN: < %s | FileCheck %s --check-prefix=CHECK-P9 \
; RUN: --implicit-check-not xxswapd
-; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \
+; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \
; RUN: -mattr=-power9-vector < %s | FileCheck %s
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesi32gtu.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesi32gtu.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesi32gtu.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesi32gtu.ll Tue Dec 4 12:14:57 2018
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesi32ltu.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesi32ltu.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesi32ltu.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesi32ltu.ll Tue Dec 4 12:14:57 2018
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesieqsc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesieqsc.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesieqsc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesieqsc.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; ModuleID = 'ComparisonTestCases/testComparesieqsc.c'
@@ -17,6 +17,19 @@ define signext i32 @test_ieqsc(i8 signex
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ieqsc:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ieqsc:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%conv2 = zext i1 %cmp to i32
@@ -32,6 +45,21 @@ define signext i32 @test_ieqsc_sext(i8 s
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ieqsc_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ieqsc_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%sub = sext i1 %cmp to i32
@@ -45,6 +73,17 @@ define signext i32 @test_ieqsc_z(i8 sign
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ieqsc_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ieqsc_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv1 = zext i1 %cmp to i32
@@ -59,6 +98,19 @@ define signext i32 @test_ieqsc_sext_z(i8
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ieqsc_sext_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ieqsc_sext_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%sub = sext i1 %cmp to i32
@@ -69,13 +121,30 @@ entry:
define void @test_ieqsc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ieqsc_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: stb r3, 0(r4)
+; CHECK-NEXT: stb r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ieqsc_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: stb r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ieqsc_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: stb r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%conv3 = zext i1 %cmp to i8
@@ -87,14 +156,33 @@ entry:
define void @test_ieqsc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ieqsc_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
-; CHECK-NEXT: stb r3, 0(r4)
+; CHECK-NEXT: stb r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ieqsc_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: stb r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ieqsc_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: stb r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%conv3 = sext i1 %cmp to i8
@@ -106,12 +194,27 @@ entry:
define void @test_ieqsc_z_store(i8 signext %a) {
; CHECK-LABEL: test_ieqsc_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: stb r3, 0(r4)
+; CHECK-NEXT: stb r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ieqsc_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: stb r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ieqsc_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: stb r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv2 = zext i1 %cmp to i8
@@ -123,13 +226,30 @@ entry:
define void @test_ieqsc_sext_z_store(i8 signext %a) {
; CHECK-LABEL: test_ieqsc_sext_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
-; CHECK-NEXT: stb r3, 0(r4)
+; CHECK-NEXT: stb r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ieqsc_sext_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: stb r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ieqsc_sext_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: stb r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv2 = sext i1 %cmp to i8
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesieqsi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesieqsi.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesieqsi.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesieqsi.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; ModuleID = 'ComparisonTestCases/testComparesieqsi.c'
@@ -17,6 +17,19 @@ define signext i32 @test_ieqsi(i32 signe
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ieqsi:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ieqsi:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%conv = zext i1 %cmp to i32
@@ -32,6 +45,21 @@ define signext i32 @test_ieqsi_sext(i32
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ieqsi_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ieqsi_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%sub = sext i1 %cmp to i32
@@ -45,6 +73,17 @@ define signext i32 @test_ieqsi_z(i32 sig
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ieqsi_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ieqsi_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%conv = zext i1 %cmp to i32
@@ -59,6 +98,19 @@ define signext i32 @test_ieqsi_sext_z(i3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ieqsi_sext_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ieqsi_sext_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%sub = sext i1 %cmp to i32
@@ -69,13 +121,30 @@ entry:
define void @test_ieqsi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ieqsi_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: stw r3, 0(r4)
+; CHECK-NEXT: stw r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ieqsi_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: stw r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ieqsi_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: stw r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%conv = zext i1 %cmp to i32
@@ -87,14 +156,33 @@ entry:
define void @test_ieqsi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ieqsi_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
-; CHECK-NEXT: stw r3, 0(r4)
+; CHECK-NEXT: stw r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ieqsi_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: stw r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ieqsi_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: stw r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%sub = sext i1 %cmp to i32
@@ -106,12 +194,27 @@ entry:
define void @test_ieqsi_z_store(i32 signext %a) {
; CHECK-LABEL: test_ieqsi_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: stw r3, 0(r4)
+; CHECK-NEXT: stw r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ieqsi_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: stw r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ieqsi_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: stw r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%conv = zext i1 %cmp to i32
@@ -123,13 +226,30 @@ entry:
define void @test_ieqsi_sext_z_store(i32 signext %a) {
; CHECK-LABEL: test_ieqsi_sext_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
-; CHECK-NEXT: stw r3, 0(r4)
+; CHECK-NEXT: stw r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ieqsi_sext_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: stw r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ieqsi_sext_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: stw r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%sub = sext i1 %cmp to i32
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesieqsll.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesieqsll.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesieqsll.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesieqsll.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; ModuleID = 'ComparisonTestCases/testComparesieqsll.c'
@@ -17,6 +17,19 @@ define signext i32 @test_ieqsll(i64 %a,
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ieqsll:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzd r3, r3
+; CHECK-BE-NEXT: rldicl r3, r3, 58, 63
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ieqsll:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzd r3, r3
+; CHECK-LE-NEXT: rldicl r3, r3, 58, 63
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%conv = zext i1 %cmp to i32
@@ -31,6 +44,19 @@ define signext i32 @test_ieqsll_sext(i64
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ieqsll_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: addic r3, r3, -1
+; CHECK-BE-NEXT: subfe r3, r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ieqsll_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addic r3, r3, -1
+; CHECK-LE-NEXT: subfe r3, r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%sub = sext i1 %cmp to i32
@@ -44,6 +70,17 @@ define signext i32 @test_ieqsll_z(i64 %a
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ieqsll_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzd r3, r3
+; CHECK-BE-NEXT: rldicl r3, r3, 58, 63
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ieqsll_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzd r3, r3
+; CHECK-LE-NEXT: rldicl r3, r3, 58, 63
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%conv = zext i1 %cmp to i32
@@ -57,6 +94,17 @@ define signext i32 @test_ieqsll_sext_z(i
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ieqsll_sext_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addic r3, r3, -1
+; CHECK-BE-NEXT: subfe r3, r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ieqsll_sext_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: addic r3, r3, -1
+; CHECK-LE-NEXT: subfe r3, r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%sub = sext i1 %cmp to i32
@@ -67,13 +115,30 @@ entry:
define void @test_ieqsll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_ieqsll_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ieqsll_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: cntlzd r3, r3
+; CHECK-BE-NEXT: rldicl r3, r3, 58, 63
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ieqsll_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzd r3, r3
+; CHECK-LE-NEXT: rldicl r3, r3, 58, 63
+; CHECK-LE-NEXT: std r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%conv1 = zext i1 %cmp to i64
@@ -85,13 +150,30 @@ entry:
define void @test_ieqsll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_ieqsll_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ieqsll_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: addic r3, r3, -1
+; CHECK-BE-NEXT: subfe r3, r3, r3
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ieqsll_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: addic r3, r3, -1
+; CHECK-LE-NEXT: subfe r3, r3, r3
+; CHECK-LE-NEXT: std r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%conv1 = sext i1 %cmp to i64
@@ -103,12 +185,27 @@ entry:
define void @test_ieqsll_z_store(i64 %a) {
; CHECK-LABEL: test_ieqsll_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: cntlzd r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 58, 63
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ieqsll_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzd r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: rldicl r3, r3, 58, 63
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ieqsll_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzd r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: rldicl r3, r3, 58, 63
+; CHECK-LE-NEXT: std r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%conv1 = zext i1 %cmp to i64
@@ -120,12 +217,27 @@ entry:
define void @test_ieqsll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_ieqsll_sext_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: addic r3, r3, -1
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: subfe r3, r3, r3
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ieqsll_sext_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: addic r3, r3, -1
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: subfe r3, r3, r3
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ieqsll_sext_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: addic r3, r3, -1
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: subfe r3, r3, r3
+; CHECK-LE-NEXT: std r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%conv1 = sext i1 %cmp to i64
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesieqss.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesieqss.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesieqss.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesieqss.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; ModuleID = 'ComparisonTestCases/testComparesieqss.c'
@@ -17,6 +17,19 @@ define signext i32 @test_ieqss(i16 signe
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ieqss:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ieqss:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%conv2 = zext i1 %cmp to i32
@@ -32,6 +45,21 @@ define signext i32 @test_ieqss_sext(i16
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ieqss_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ieqss_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%sub = sext i1 %cmp to i32
@@ -45,6 +73,17 @@ define signext i32 @test_ieqss_z(i16 sig
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ieqss_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ieqss_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%conv1 = zext i1 %cmp to i32
@@ -59,6 +98,19 @@ define signext i32 @test_ieqss_sext_z(i1
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ieqss_sext_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ieqss_sext_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%sub = sext i1 %cmp to i32
@@ -69,13 +121,30 @@ entry:
define void @test_ieqss_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_ieqss_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: sth r3, 0(r4)
+; CHECK-NEXT: sth r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ieqss_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ieqss_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: sth r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%conv3 = zext i1 %cmp to i16
@@ -87,14 +156,33 @@ entry:
define void @test_ieqss_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_ieqss_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
-; CHECK-NEXT: sth r3, 0(r4)
+; CHECK-NEXT: sth r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ieqss_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ieqss_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: sth r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%conv3 = sext i1 %cmp to i16
@@ -106,12 +194,27 @@ entry:
define void @test_ieqss_z_store(i16 signext %a) {
; CHECK-LABEL: test_ieqss_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: sth r3, 0(r4)
+; CHECK-NEXT: sth r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ieqss_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ieqss_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: sth r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%conv2 = zext i1 %cmp to i16
@@ -123,13 +226,30 @@ entry:
define void @test_ieqss_sext_z_store(i16 signext %a) {
; CHECK-LABEL: test_ieqss_sext_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
-; CHECK-NEXT: sth r3, 0(r4)
+; CHECK-NEXT: sth r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ieqss_sext_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ieqss_sext_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: sth r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%conv2 = sext i1 %cmp to i16
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesiequc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesiequc.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesiequc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesiequc.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; ModuleID = 'ComparisonTestCases/testComparesiequc.c'
@@ -17,6 +17,19 @@ define signext i32 @test_iequc(i8 zeroex
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequc:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequc:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%conv2 = zext i1 %cmp to i32
@@ -32,6 +45,21 @@ define signext i32 @test_iequc_sext(i8 z
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequc_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequc_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%sub = sext i1 %cmp to i32
@@ -45,6 +73,17 @@ define signext i32 @test_iequc_z(i8 zero
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequc_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequc_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv1 = zext i1 %cmp to i32
@@ -59,6 +98,19 @@ define signext i32 @test_iequc_sext_z(i8
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequc_sext_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequc_sext_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%sub = sext i1 %cmp to i32
@@ -69,13 +121,30 @@ entry:
define void @test_iequc_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_iequc_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: stb r3, 0(r4)
+; CHECK-NEXT: stb r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequc_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: stb r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequc_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: stb r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%conv3 = zext i1 %cmp to i8
@@ -87,14 +156,33 @@ entry:
define void @test_iequc_sext_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_iequc_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
-; CHECK-NEXT: stb r3, 0(r4)
+; CHECK-NEXT: stb r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequc_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: stb r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequc_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: stb r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%conv3 = sext i1 %cmp to i8
@@ -106,12 +194,27 @@ entry:
define void @test_iequc_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_iequc_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: stb r3, 0(r4)
+; CHECK-NEXT: stb r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequc_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: stb r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequc_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: stb r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv2 = zext i1 %cmp to i8
@@ -123,13 +226,30 @@ entry:
define void @test_iequc_sext_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_iequc_sext_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
-; CHECK-NEXT: stb r3, 0(r4)
+; CHECK-NEXT: stb r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequc_sext_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: stb r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequc_sext_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: stb r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv2 = sext i1 %cmp to i8
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesiequi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesiequi.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesiequi.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesiequi.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; ModuleID = 'ComparisonTestCases/testComparesiequi.c'
@@ -17,6 +17,19 @@ define signext i32 @test_iequi(i32 zeroe
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequi:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequi:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%conv = zext i1 %cmp to i32
@@ -32,6 +45,21 @@ define signext i32 @test_iequi_sext(i32
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequi_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequi_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%sub = sext i1 %cmp to i32
@@ -45,6 +73,17 @@ define signext i32 @test_iequi_z(i32 zer
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequi_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequi_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%conv = zext i1 %cmp to i32
@@ -59,6 +98,19 @@ define signext i32 @test_iequi_sext_z(i3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequi_sext_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequi_sext_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%sub = sext i1 %cmp to i32
@@ -69,13 +121,30 @@ entry:
define void @test_iequi_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_iequi_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: stw r3, 0(r4)
+; CHECK-NEXT: stw r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequi_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: stw r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequi_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: stw r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%conv = zext i1 %cmp to i32
@@ -87,14 +156,33 @@ entry:
define void @test_iequi_sext_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_iequi_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
-; CHECK-NEXT: stw r3, 0(r4)
+; CHECK-NEXT: stw r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequi_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: stw r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequi_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: stw r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%sub = sext i1 %cmp to i32
@@ -106,12 +194,27 @@ entry:
define void @test_iequi_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_iequi_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: stw r3, 0(r4)
+; CHECK-NEXT: stw r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequi_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: stw r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequi_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: stw r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%conv = zext i1 %cmp to i32
@@ -123,13 +226,30 @@ entry:
define void @test_iequi_sext_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_iequi_sext_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
-; CHECK-NEXT: stw r3, 0(r4)
+; CHECK-NEXT: stw r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequi_sext_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: stw r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequi_sext_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: stw r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%sub = sext i1 %cmp to i32
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesiequll.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesiequll.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesiequll.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesiequll.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; ModuleID = 'ComparisonTestCases/testComparesiequll.c'
@@ -17,6 +17,19 @@ define signext i32 @test_iequll(i64 %a,
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequll:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzd r3, r3
+; CHECK-BE-NEXT: rldicl r3, r3, 58, 63
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequll:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzd r3, r3
+; CHECK-LE-NEXT: rldicl r3, r3, 58, 63
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%conv = zext i1 %cmp to i32
@@ -31,6 +44,19 @@ define signext i32 @test_iequll_sext(i64
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequll_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: addic r3, r3, -1
+; CHECK-BE-NEXT: subfe r3, r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequll_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addic r3, r3, -1
+; CHECK-LE-NEXT: subfe r3, r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%sub = sext i1 %cmp to i32
@@ -44,6 +70,17 @@ define signext i32 @test_iequll_z(i64 %a
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequll_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzd r3, r3
+; CHECK-BE-NEXT: rldicl r3, r3, 58, 63
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequll_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzd r3, r3
+; CHECK-LE-NEXT: rldicl r3, r3, 58, 63
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%conv = zext i1 %cmp to i32
@@ -57,6 +94,17 @@ define signext i32 @test_iequll_sext_z(i
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequll_sext_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addic r3, r3, -1
+; CHECK-BE-NEXT: subfe r3, r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequll_sext_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: addic r3, r3, -1
+; CHECK-LE-NEXT: subfe r3, r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%sub = sext i1 %cmp to i32
@@ -67,13 +115,30 @@ entry:
define void @test_iequll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_iequll_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequll_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: cntlzd r3, r3
+; CHECK-BE-NEXT: rldicl r3, r3, 58, 63
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequll_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzd r3, r3
+; CHECK-LE-NEXT: rldicl r3, r3, 58, 63
+; CHECK-LE-NEXT: std r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%conv1 = zext i1 %cmp to i64
@@ -85,13 +150,30 @@ entry:
define void @test_iequll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_iequll_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequll_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: addic r3, r3, -1
+; CHECK-BE-NEXT: subfe r3, r3, r3
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequll_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: addic r3, r3, -1
+; CHECK-LE-NEXT: subfe r3, r3, r3
+; CHECK-LE-NEXT: std r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%conv1 = sext i1 %cmp to i64
@@ -103,12 +185,27 @@ entry:
define void @test_iequll_z_store(i64 %a) {
; CHECK-LABEL: test_iequll_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: cntlzd r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 58, 63
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequll_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzd r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: rldicl r3, r3, 58, 63
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequll_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzd r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: rldicl r3, r3, 58, 63
+; CHECK-LE-NEXT: std r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%conv1 = zext i1 %cmp to i64
@@ -120,12 +217,27 @@ entry:
define void @test_iequll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_iequll_sext_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: addic r3, r3, -1
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: subfe r3, r3, r3
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequll_sext_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: addic r3, r3, -1
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: subfe r3, r3, r3
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequll_sext_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: addic r3, r3, -1
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: subfe r3, r3, r3
+; CHECK-LE-NEXT: std r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%conv1 = sext i1 %cmp to i64
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesiequs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesiequs.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesiequs.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesiequs.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; ModuleID = 'ComparisonTestCases/testComparesiequs.c'
@@ -17,6 +17,19 @@ define signext i32 @test_iequs(i16 zeroe
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequs:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequs:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%conv2 = zext i1 %cmp to i32
@@ -32,6 +45,21 @@ define signext i32 @test_iequs_sext(i16
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequs_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequs_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%sub = sext i1 %cmp to i32
@@ -45,6 +73,17 @@ define signext i32 @test_iequs_z(i16 zer
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequs_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequs_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%conv1 = zext i1 %cmp to i32
@@ -59,6 +98,19 @@ define signext i32 @test_iequs_sext_z(i1
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequs_sext_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequs_sext_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%sub = sext i1 %cmp to i32
@@ -69,13 +121,30 @@ entry:
define void @test_iequs_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_iequs_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: sth r3, 0(r4)
+; CHECK-NEXT: sth r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequs_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequs_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: sth r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%conv3 = zext i1 %cmp to i16
@@ -87,14 +156,33 @@ entry:
define void @test_iequs_sext_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_iequs_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
-; CHECK-NEXT: sth r3, 0(r4)
+; CHECK-NEXT: sth r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequs_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequs_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: sth r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%conv3 = sext i1 %cmp to i16
@@ -106,12 +194,27 @@ entry:
define void @test_iequs_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_iequs_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: sth r3, 0(r4)
+; CHECK-NEXT: sth r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequs_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequs_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: sth r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%conv2 = zext i1 %cmp to i16
@@ -123,13 +226,30 @@ entry:
define void @test_iequs_sext_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_iequs_sext_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
-; CHECK-NEXT: sth r3, 0(r4)
+; CHECK-NEXT: sth r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequs_sext_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequs_sext_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: sth r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%conv2 = sext i1 %cmp to i16
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesigesc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigesc.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesigesc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesigesc.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i8 0, align 1
@@ -14,6 +14,19 @@ define signext i32 @test_igesc(i8 signex
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_igesc:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sub r3, r3, r4
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_igesc:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r3, r4
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
%conv2 = zext i1 %cmp to i32
@@ -27,6 +40,19 @@ define signext i32 @test_igesc_sext(i8 s
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_igesc_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sub r3, r3, r4
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: addi r3, r3, -1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_igesc_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r3, r4
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: addi r3, r3, -1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
%sub = sext i1 %cmp to i32
@@ -36,13 +62,30 @@ entry:
define void @test_igesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igesc_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
-; CHECK-NEXT: stb r3, 0(r4)
+; CHECK-NEXT: stb r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_igesc_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: sub r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: stb r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_igesc_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: stb r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
%conv3 = zext i1 %cmp to i8
@@ -53,13 +96,30 @@ entry:
define void @test_igesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igesc_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
-; CHECK-NEXT: stb r3, 0(r4)
+; CHECK-NEXT: stb r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_igesc_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: sub r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: addi r3, r3, -1
+; CHECK-BE-NEXT: stb r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_igesc_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: addi r3, r3, -1
+; CHECK-LE-NEXT: stb r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
%conv3 = sext i1 %cmp to i8
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesigesi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigesi.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesigesi.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesigesi.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i32 0, align 4
@@ -14,6 +14,19 @@ define signext i32 @test_igesi(i32 signe
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_igesi:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sub r3, r3, r4
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_igesi:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r3, r4
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%conv = zext i1 %cmp to i32
@@ -27,6 +40,19 @@ define signext i32 @test_igesi_sext(i32
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_igesi_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sub r3, r3, r4
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: addi r3, r3, -1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_igesi_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r3, r4
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: addi r3, r3, -1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%sub = sext i1 %cmp to i32
@@ -36,13 +62,30 @@ entry:
define void @test_igesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igesi_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
-; CHECK-NEXT: stw r3, 0(r4)
+; CHECK-NEXT: stw r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_igesi_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: sub r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: stw r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_igesi_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: stw r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%conv = zext i1 %cmp to i32
@@ -53,13 +96,30 @@ entry:
define void @test_igesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igesi_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
-; CHECK-NEXT: stw r3, 0(r4)
+; CHECK-NEXT: stw r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_igesi_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: sub r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: addi r3, r3, -1
+; CHECK-BE-NEXT: stw r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_igesi_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: addi r3, r3, -1
+; CHECK-LE-NEXT: stw r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%sub = sext i1 %cmp to i32
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesigesll.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigesll.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesigesll.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesigesll.ll Tue Dec 4 12:14:57 2018
@@ -1,10 +1,10 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i64 0, align 8
define signext i32 @test_igesll(i64 %a, i64 %b) {
@@ -15,6 +15,21 @@ define signext i32 @test_igesll(i64 %a,
; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_igesll:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sradi r5, r3, 63
+; CHECK-BE-NEXT: rldicl r6, r4, 1, 63
+; CHECK-BE-NEXT: subfc r3, r4, r3
+; CHECK-BE-NEXT: adde r3, r5, r6
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_igesll:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sradi r5, r3, 63
+; CHECK-LE-NEXT: rldicl r6, r4, 1, 63
+; CHECK-LE-NEXT: subfc r3, r4, r3
+; CHECK-LE-NEXT: adde r3, r5, r6
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i64 %a, %b
%conv = zext i1 %cmp to i32
@@ -30,6 +45,23 @@ define signext i32 @test_igesll_sext(i64
; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_igesll_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sradi r5, r3, 63
+; CHECK-BE-NEXT: rldicl r6, r4, 1, 63
+; CHECK-BE-NEXT: subfc r3, r4, r3
+; CHECK-BE-NEXT: adde r3, r5, r6
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_igesll_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sradi r5, r3, 63
+; CHECK-LE-NEXT: rldicl r6, r4, 1, 63
+; CHECK-LE-NEXT: subfc r3, r4, r3
+; CHECK-LE-NEXT: adde r3, r5, r6
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i64 %a, %b
%sub = sext i1 %cmp to i32
@@ -42,6 +74,17 @@ define signext i32 @test_igesll_z(i64 %a
; CHECK-NEXT: not r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_igesll_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: not r3, r3
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_igesll_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: not r3, r3
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, -1
%conv = zext i1 %cmp to i32
@@ -54,6 +97,17 @@ define signext i32 @test_igesll_sext_z(i
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: not r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_igesll_sext_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sradi r3, r3, 63
+; CHECK-BE-NEXT: not r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_igesll_sext_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sradi r3, r3, 63
+; CHECK-LE-NEXT: not r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, -1
%sub = sext i1 %cmp to i32
@@ -63,12 +117,33 @@ entry:
define void @test_igesll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_igesll_store:
; CHECK: # %bb.0: # %entry
-; CHECK: sradi r6, r3, 63
-; CHECK: subfc r3, r4, r3
-; CHECK: rldicl r3, r4, 1, 63
-; CHECK: adde r3, r6, r3
-; CHECK: std r3
+; CHECK-NEXT: sradi r6, r3, 63
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-NEXT: subfc r3, r4, r3
+; CHECK-NEXT: rldicl r3, r4, 1, 63
+; CHECK-NEXT: adde r3, r6, r3
+; CHECK-NEXT: std r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_igesll_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: sradi r6, r3, 63
+; CHECK-BE-NEXT: ld r5, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: subfc r3, r4, r3
+; CHECK-BE-NEXT: rldicl r3, r4, 1, 63
+; CHECK-BE-NEXT: adde r3, r6, r3
+; CHECK-BE-NEXT: std r3, 0(r5)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_igesll_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sradi r6, r3, 63
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: subfc r3, r4, r3
+; CHECK-LE-NEXT: rldicl r3, r4, 1, 63
+; CHECK-LE-NEXT: adde r3, r6, r3
+; CHECK-LE-NEXT: std r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i64 %a, %b
%conv1 = zext i1 %cmp to i64
@@ -80,14 +155,35 @@ define void @test_igesll_sext_store(i64
; CHECK-LABEL: test_igesll_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r6, r3, 63
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: rldicl r3, r4, 1, 63
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: adde r3, r6, r3
; CHECK-NEXT: neg r3, r3
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_igesll_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sradi r6, r3, 63
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: subfc r3, r4, r3
+; CHECK-BE-NEXT: rldicl r3, r4, 1, 63
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: adde r3, r6, r3
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_igesll_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sradi r6, r3, 63
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: subfc r3, r4, r3
+; CHECK-LE-NEXT: rldicl r3, r4, 1, 63
+; CHECK-LE-NEXT: adde r3, r6, r3
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: std r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i64 %a, %b
%conv1 = sext i1 %cmp to i64
@@ -98,12 +194,27 @@ entry:
define void @test_igesll_z_store(i64 %a) {
; CHECK-LABEL: test_igesll_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: not r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_igesll_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: not r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_igesll_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: not r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: std r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, -1
%conv1 = zext i1 %cmp to i64
@@ -114,12 +225,27 @@ entry:
define void @test_igesll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_igesll_sext_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: not r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: sradi r3, r3, 63
-; CHECK-NEXT: std r3,
+; CHECK-NEXT: std r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_igesll_sext_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: not r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: sradi r3, r3, 63
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_igesll_sext_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: not r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: sradi r3, r3, 63
+; CHECK-LE-NEXT: std r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, -1
%conv1 = sext i1 %cmp to i64
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesigess.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigess.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesigess.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesigess.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i16 0, align 2
@@ -14,6 +14,19 @@ define signext i32 @test_igess(i16 signe
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_igess:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sub r3, r3, r4
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_igess:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r3, r4
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
%conv2 = zext i1 %cmp to i32
@@ -27,6 +40,19 @@ define signext i32 @test_igess_sext(i16
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_igess_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sub r3, r3, r4
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: addi r3, r3, -1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_igess_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r3, r4
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: addi r3, r3, -1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
%sub = sext i1 %cmp to i32
@@ -36,13 +62,30 @@ entry:
define void @test_igess_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igess_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
-; CHECK-NEXT: sth r3, 0(r4)
+; CHECK-NEXT: sth r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_igess_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: sub r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_igess_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: sth r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
%conv3 = zext i1 %cmp to i16
@@ -53,13 +96,30 @@ entry:
define void @test_igess_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igess_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
-; CHECK-NEXT: sth r3, 0(r4)
+; CHECK-NEXT: sth r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_igess_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: sub r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: addi r3, r3, -1
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_igess_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: addi r3, r3, -1
+; CHECK-LE-NEXT: sth r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
%conv3 = sext i1 %cmp to i16
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesigtsc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigtsc.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesigtsc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesigtsc.ll Tue Dec 4 12:14:57 2018
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesigtsi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigtsi.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesigtsi.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesigtsi.ll Tue Dec 4 12:14:57 2018
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesigtsll.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigtsll.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesigtsll.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesigtsll.ll Tue Dec 4 12:14:57 2018
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesigtss.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigtss.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesigtss.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesigtss.ll Tue Dec 4 12:14:57 2018
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesigtuc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigtuc.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesigtuc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesigtuc.ll Tue Dec 4 12:14:57 2018
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesigtui.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigtui.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesigtui.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesigtui.ll Tue Dec 4 12:14:57 2018
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesigtus.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigtus.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesigtus.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesigtus.ll Tue Dec 4 12:14:57 2018
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesilesc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesilesc.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesilesc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesilesc.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i8 0, align 1
@@ -14,6 +14,19 @@ define signext i32 @test_ilesc(i8 signex
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ilesc:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sub r3, r4, r3
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ilesc:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r4, r3
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
%conv2 = zext i1 %cmp to i32
@@ -27,6 +40,19 @@ define signext i32 @test_ilesc_sext(i8 s
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ilesc_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sub r3, r4, r3
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: addi r3, r3, -1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ilesc_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r4, r3
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: addi r3, r3, -1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
%sub = sext i1 %cmp to i32
@@ -36,13 +62,30 @@ entry:
define void @test_ilesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ilesc_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r4, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
-; CHECK-NEXT: stb r3, 0(r4)
+; CHECK-NEXT: stb r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ilesc_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: sub r3, r4, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: stb r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ilesc_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r4, r3
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: stb r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
%conv3 = zext i1 %cmp to i8
@@ -53,13 +96,30 @@ entry:
define void @test_ilesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ilesc_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r4, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
-; CHECK-NEXT: stb r3, 0(r4)
+; CHECK-NEXT: stb r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ilesc_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: sub r3, r4, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: addi r3, r3, -1
+; CHECK-BE-NEXT: stb r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ilesc_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r4, r3
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: addi r3, r3, -1
+; CHECK-LE-NEXT: stb r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
%conv3 = sext i1 %cmp to i8
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesilesi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesilesi.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesilesi.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesilesi.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i32 0, align 4
@@ -14,6 +14,19 @@ define signext i32 @test_ilesi(i32 signe
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ilesi:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sub r3, r4, r3
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ilesi:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r4, r3
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
%conv = zext i1 %cmp to i32
@@ -27,6 +40,19 @@ define signext i32 @test_ilesi_sext(i32
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ilesi_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sub r3, r4, r3
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: addi r3, r3, -1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ilesi_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r4, r3
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: addi r3, r3, -1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
%sub = sext i1 %cmp to i32
@@ -36,13 +62,30 @@ entry:
define void @test_ilesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ilesi_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r4, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
-; CHECK-NEXT: stw r3, 0(r4)
+; CHECK-NEXT: stw r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ilesi_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: sub r3, r4, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: stw r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ilesi_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r4, r3
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: stw r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
%conv = zext i1 %cmp to i32
@@ -53,13 +96,30 @@ entry:
define void @test_ilesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ilesi_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r4, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
-; CHECK-NEXT: stw r3, 0(r4)
+; CHECK-NEXT: stw r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ilesi_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: sub r3, r4, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: addi r3, r3, -1
+; CHECK-BE-NEXT: stw r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ilesi_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r4, r3
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: addi r3, r3, -1
+; CHECK-LE-NEXT: stw r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
%sub = sext i1 %cmp to i32
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesilesll.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesilesll.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesilesll.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesilesll.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i64 0, align 8
@@ -15,6 +15,21 @@ define signext i32 @test_ilesll(i64 %a,
; CHECK-NEXT: subfc r3, r3, r4
; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ilesll:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sradi r5, r4, 63
+; CHECK-BE-NEXT: rldicl r6, r3, 1, 63
+; CHECK-BE-NEXT: subfc r3, r3, r4
+; CHECK-BE-NEXT: adde r3, r5, r6
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ilesll:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sradi r5, r4, 63
+; CHECK-LE-NEXT: rldicl r6, r3, 1, 63
+; CHECK-LE-NEXT: subfc r3, r3, r4
+; CHECK-LE-NEXT: adde r3, r5, r6
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sle i64 %a, %b
%conv = zext i1 %cmp to i32
@@ -30,6 +45,23 @@ define signext i32 @test_ilesll_sext(i64
; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ilesll_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sradi r5, r4, 63
+; CHECK-BE-NEXT: rldicl r6, r3, 1, 63
+; CHECK-BE-NEXT: subfc r3, r3, r4
+; CHECK-BE-NEXT: adde r3, r5, r6
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ilesll_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sradi r5, r4, 63
+; CHECK-LE-NEXT: rldicl r6, r3, 1, 63
+; CHECK-LE-NEXT: subfc r3, r3, r4
+; CHECK-LE-NEXT: adde r3, r5, r6
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sle i64 %a, %b
%sub = sext i1 %cmp to i32
@@ -43,6 +75,19 @@ define signext i32 @test_ilesll_z(i64 %a
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ilesll_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addi r4, r3, -1
+; CHECK-BE-NEXT: or r3, r4, r3
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ilesll_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: addi r4, r3, -1
+; CHECK-LE-NEXT: or r3, r4, r3
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp slt i64 %a, 1
%conv = zext i1 %cmp to i32
@@ -56,6 +101,19 @@ define signext i32 @test_ilesll_sext_z(i
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ilesll_sext_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addi r4, r3, -1
+; CHECK-BE-NEXT: or r3, r4, r3
+; CHECK-BE-NEXT: sradi r3, r3, 63
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ilesll_sext_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: addi r4, r3, -1
+; CHECK-LE-NEXT: or r3, r4, r3
+; CHECK-LE-NEXT: sradi r3, r3, 63
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp slt i64 %a, 1
%sub = sext i1 %cmp to i32
@@ -65,14 +123,33 @@ entry:
define void @test_ilesll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_ilesll_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sradi r6, r4, 63
-; CHECK-NEXT: ld r5, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: subfc r4, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: adde r3, r6, r3
-; CHECK-NEXT: std r3, 0(r5)
+; CHECK-NEXT: std r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ilesll_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: sradi r6, r4, 63
+; CHECK-BE-NEXT: ld r5, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: subfc r4, r3, r4
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: adde r3, r6, r3
+; CHECK-BE-NEXT: std r3, 0(r5)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ilesll_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sradi r6, r4, 63
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: subfc r4, r3, r4
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: adde r3, r6, r3
+; CHECK-LE-NEXT: std r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sle i64 %a, %b
%conv1 = zext i1 %cmp to i64
@@ -84,14 +161,35 @@ define void @test_ilesll_sext_store(i64
; CHECK-LABEL: test_ilesll_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r6, r4, 63
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: subfc r4, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: adde r3, r6, r3
; CHECK-NEXT: neg r3, r3
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ilesll_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sradi r6, r4, 63
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: subfc r4, r3, r4
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: adde r3, r6, r3
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ilesll_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sradi r6, r4, 63
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: subfc r4, r3, r4
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: adde r3, r6, r3
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: std r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sle i64 %a, %b
%conv1 = sext i1 %cmp to i64
@@ -102,13 +200,30 @@ entry:
define void @test_ilesll_z_store(i64 %a) {
; CHECK-LABEL: test_ilesll_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: addi r5, r3, -1
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: or r3, r5, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ilesll_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: addi r5, r3, -1
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: or r3, r5, r3
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ilesll_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: addi r5, r3, -1
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: or r3, r5, r3
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: std r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp slt i64 %a, 1
%conv1 = zext i1 %cmp to i64
@@ -119,13 +234,30 @@ entry:
define void @test_ilesll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_ilesll_sext_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: addi r5, r3, -1
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: or r3, r5, r3
; CHECK-NEXT: sradi r3, r3, 63
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ilesll_sext_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: addi r5, r3, -1
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: or r3, r5, r3
+; CHECK-BE-NEXT: sradi r3, r3, 63
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ilesll_sext_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: addi r5, r3, -1
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: or r3, r5, r3
+; CHECK-LE-NEXT: sradi r3, r3, 63
+; CHECK-LE-NEXT: std r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp slt i64 %a, 1
%conv1 = sext i1 %cmp to i64
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesiless.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesiless.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesiless.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesiless.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i16 0, align 2
@@ -14,6 +14,19 @@ define signext i32 @test_iless(i16 signe
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iless:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sub r3, r4, r3
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iless:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r4, r3
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
%conv2 = zext i1 %cmp to i32
@@ -27,6 +40,19 @@ define signext i32 @test_iless_sext(i16
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iless_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sub r3, r4, r3
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: addi r3, r3, -1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iless_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r4, r3
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: addi r3, r3, -1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
%sub = sext i1 %cmp to i32
@@ -36,13 +62,30 @@ entry:
define void @test_iless_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iless_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r4, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
-; CHECK-NEXT: sth r3, 0(r4)
+; CHECK-NEXT: sth r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iless_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: sub r3, r4, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iless_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r4, r3
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: sth r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
%conv3 = zext i1 %cmp to i16
@@ -53,13 +96,30 @@ entry:
define void @test_iless_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iless_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r4, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
-; CHECK-NEXT: sth r3, 0(r4)
+; CHECK-NEXT: sth r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iless_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: sub r3, r4, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: addi r3, r3, -1
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iless_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r4, r3
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: addi r3, r3, -1
+; CHECK-LE-NEXT: sth r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
%conv3 = sext i1 %cmp to i16
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesinesc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesinesc.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesinesc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesinesc.ll Tue Dec 4 12:14:57 2018
@@ -1,20 +1,36 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i8 0, align 1
define signext i32 @test_inesc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_inesc:
-; CHECK: xor r3, r3, r4
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_inesc:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_inesc:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
%conv2 = zext i1 %cmp to i32
@@ -23,12 +39,30 @@ entry:
define signext i32 @test_inesc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_inesc_sext:
-; CHECK: xor r3, r3, r4
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_inesc_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_inesc_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
%sub = sext i1 %cmp to i32
@@ -37,10 +71,24 @@ entry:
define signext i32 @test_inesc_z(i8 signext %a) {
; CHECK-LABEL: test_inesc_z:
-; CHECK: cntlzw r3, r3
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_inesc_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_inesc_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%conv1 = zext i1 %cmp to i32
@@ -49,11 +97,27 @@ entry:
define signext i32 @test_inesc_sext_z(i8 signext %a) {
; CHECK-LABEL: test_inesc_sext_z:
-; CHECK: cntlzw r3, r3
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_inesc_sext_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_inesc_sext_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%sub = sext i1 %cmp to i32
@@ -62,12 +126,34 @@ entry:
define void @test_inesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_inesc_store:
-; CHECK: xor r3, r3, r4
-; CHECK: cntlzw r3, r3
-; CHECK: srwi r3, r3, 5
-; CHECK: xori r3, r3, 1
-; CHECK: stb r3, 0(r4)
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: stb r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_inesc_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: stb r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_inesc_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: stb r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
%conv3 = zext i1 %cmp to i8
@@ -77,13 +163,37 @@ entry:
define void @test_inesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_inesc_sext_store:
-; CHECK: xor r3, r3, r4
-; CHECK: cntlzw r3, r3
-; CHECK: srwi r3, r3, 5
-; CHECK: xori r3, r3, 1
-; CHECK: neg r3, r3
-; CHECK: stb r3, 0(r4)
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: stb r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_inesc_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: stb r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_inesc_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: stb r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
%conv3 = sext i1 %cmp to i8
@@ -93,11 +203,31 @@ entry:
define void @test_inesc_z_store(i8 signext %a) {
; CHECK-LABEL: test_inesc_z_store:
-; CHECK: cntlzw r3, r3
-; CHECK: srwi r3, r3, 5
-; CHECK: xori r3, r3, 1
-; CHECK: stb r3, 0(r4)
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: stb r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_inesc_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: stb r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_inesc_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: stb r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%conv2 = zext i1 %cmp to i8
@@ -107,12 +237,34 @@ entry:
define void @test_inesc_sext_z_store(i8 signext %a) {
; CHECK-LABEL: test_inesc_sext_z_store:
-; CHECK: cntlzw r3, r3
-; CHECK: srwi r3, r3, 5
-; CHECK: xori r3, r3, 1
-; CHECK: neg r3, r3
-; CHECK: stb r3, 0(r4)
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: stb r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_inesc_sext_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: stb r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_inesc_sext_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: stb r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%conv2 = sext i1 %cmp to i8
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesinesi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesinesi.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesinesi.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesinesi.ll Tue Dec 4 12:14:57 2018
@@ -1,20 +1,36 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i32 0, align 4
define signext i32 @test_inesi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_inesi:
-; CHECK: xor r3, r3, r4
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_inesi:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_inesi:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
%conv = zext i1 %cmp to i32
@@ -23,12 +39,30 @@ entry:
define signext i32 @test_inesi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_inesi_sext:
-; CHECK: xor r3, r3, r4
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_inesi_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_inesi_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
%sub = sext i1 %cmp to i32
@@ -37,10 +71,24 @@ entry:
define signext i32 @test_inesi_z(i32 signext %a) {
; CHECK-LABEL: test_inesi_z:
-; CHECK: cntlzw r3, r3
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_inesi_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_inesi_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%conv = zext i1 %cmp to i32
@@ -49,11 +97,27 @@ entry:
define signext i32 @test_inesi_sext_z(i32 signext %a) {
; CHECK-LABEL: test_inesi_sext_z:
-; CHECK: cntlzw r3, r3
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_inesi_sext_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_inesi_sext_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%sub = sext i1 %cmp to i32
@@ -62,12 +126,34 @@ entry:
define void @test_inesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_inesi_store:
-; CHECK: xor r3, r3, r4
-; CHECK: cntlzw r3, r3
-; CHECK: srwi r3, r3, 5
-; CHECK: xori r3, r3, 1
-; CHECK: stw r3, 0(r4)
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: stw r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_inesi_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: stw r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_inesi_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: stw r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
%conv = zext i1 %cmp to i32
@@ -77,13 +163,37 @@ entry:
define void @test_inesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_inesi_sext_store:
-; CHECK: xor r3, r3, r4
-; CHECK: cntlzw r3, r3
-; CHECK: srwi r3, r3, 5
-; CHECK: xori r3, r3, 1
-; CHECK: neg r3, r3
-; CHECK: stw r3, 0(r4)
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: stw r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_inesi_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: stw r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_inesi_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: stw r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
%sub = sext i1 %cmp to i32
@@ -93,11 +203,31 @@ entry:
define void @test_inesi_z_store(i32 signext %a) {
; CHECK-LABEL: test_inesi_z_store:
-; CHECK: cntlzw r3, r3
-; CHECK: srwi r3, r3, 5
-; CHECK: xori r3, r3, 1
-; CHECK: stw r3, 0(r4)
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: stw r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_inesi_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: stw r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_inesi_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: stw r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%conv = zext i1 %cmp to i32
@@ -107,12 +237,34 @@ entry:
define void @test_inesi_sext_z_store(i32 signext %a) {
; CHECK-LABEL: test_inesi_sext_z_store:
-; CHECK: cntlzw r3, r3
-; CHECK: srwi r3, r3, 5
-; CHECK: xori r3, r3, 1
-; CHECK: neg r3, r3
-; CHECK: stw r3, 0(r4)
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: stw r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_inesi_sext_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: stw r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_inesi_sext_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: stw r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%sub = sext i1 %cmp to i32
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesinesll.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesinesll.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesinesll.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesinesll.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i64 0, align 8
@@ -15,6 +15,19 @@ define signext i32 @test_inesll(i64 %a,
; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_inesll:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: addic r4, r3, -1
+; CHECK-BE-NEXT: subfe r3, r4, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_inesll:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addic r4, r3, -1
+; CHECK-LE-NEXT: subfe r3, r4, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv = zext i1 %cmp to i32
@@ -28,6 +41,19 @@ define signext i32 @test_inesll_sext(i64
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_inesll_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: subfic r3, r3, 0
+; CHECK-BE-NEXT: subfe r3, r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_inesll_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: subfic r3, r3, 0
+; CHECK-LE-NEXT: subfe r3, r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%sub = sext i1 %cmp to i32
@@ -40,6 +66,17 @@ define signext i32 @test_inesll_z(i64 %a
; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_inesll_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addic r4, r3, -1
+; CHECK-BE-NEXT: subfe r3, r4, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_inesll_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: addic r4, r3, -1
+; CHECK-LE-NEXT: subfe r3, r4, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv = zext i1 %cmp to i32
@@ -52,6 +89,17 @@ define signext i32 @test_inesll_sext_z(i
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_inesll_sext_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: subfic r3, r3, 0
+; CHECK-BE-NEXT: subfe r3, r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_inesll_sext_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: subfic r3, r3, 0
+; CHECK-LE-NEXT: subfe r3, r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%sub = sext i1 %cmp to i32
@@ -61,13 +109,30 @@ entry:
define void @test_inesll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_inesll_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
-; CHECK-NEXT: addic r5, r3, -1
-; CHECK-NEXT: subfe r3, r5, r3
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-NEXT: addic r4, r3, -1
+; CHECK-NEXT: subfe r3, r4, r3
+; CHECK-NEXT: std r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_inesll_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: addic r5, r3, -1
+; CHECK-BE-NEXT: subfe r3, r5, r3
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_inesll_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: addic r4, r3, -1
+; CHECK-LE-NEXT: subfe r3, r4, r3
+; CHECK-LE-NEXT: std r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = zext i1 %cmp to i64
@@ -78,13 +143,30 @@ entry:
define void @test_inesll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_inesll_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_inesll_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: subfic r3, r3, 0
+; CHECK-BE-NEXT: subfe r3, r3, r3
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_inesll_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: subfic r3, r3, 0
+; CHECK-LE-NEXT: subfe r3, r3, r3
+; CHECK-LE-NEXT: std r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = sext i1 %cmp to i64
@@ -95,12 +177,27 @@ entry:
define void @test_inesll_z_store(i64 %a) {
; CHECK-LABEL: test_inesll_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: addic r5, r3, -1
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: subfe r3, r5, r3
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_inesll_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: addic r5, r3, -1
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: subfe r3, r5, r3
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_inesll_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: addic r5, r3, -1
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: subfe r3, r5, r3
+; CHECK-LE-NEXT: std r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = zext i1 %cmp to i64
@@ -111,12 +208,27 @@ entry:
define void @test_inesll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_inesll_sext_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: subfic r3, r3, 0
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: subfe r3, r3, r3
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_inesll_sext_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: subfic r3, r3, 0
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: subfe r3, r3, r3
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_inesll_sext_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: subfic r3, r3, 0
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: subfe r3, r3, r3
+; CHECK-LE-NEXT: std r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = sext i1 %cmp to i64
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesiness.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesiness.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesiness.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesiness.ll Tue Dec 4 12:14:57 2018
@@ -1,20 +1,36 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i16 0, align 2
define signext i32 @test_iness(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iness:
-; CHECK: xor r3, r3, r4
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iness:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iness:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
%conv2 = zext i1 %cmp to i32
@@ -23,12 +39,30 @@ entry:
define signext i32 @test_iness_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iness_sext:
-; CHECK: xor r3, r3, r4
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iness_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iness_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
%sub = sext i1 %cmp to i32
@@ -37,10 +71,24 @@ entry:
define signext i32 @test_iness_z(i16 signext %a) {
; CHECK-LABEL: test_iness_z:
-; CHECK: cntlzw r3, r3
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iness_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iness_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%conv1 = zext i1 %cmp to i32
@@ -49,11 +97,27 @@ entry:
define signext i32 @test_iness_sext_z(i16 signext %a) {
; CHECK-LABEL: test_iness_sext_z:
-; CHECK: cntlzw r3, r3
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iness_sext_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iness_sext_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%sub = sext i1 %cmp to i32
@@ -62,12 +126,34 @@ entry:
define void @test_iness_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iness_store:
-; CHECK: xor r3, r3, r4
-; CHECK: cntlzw r3, r3
-; CHECK: srwi r3, r3, 5
-; CHECK: xori r3, r3, 1
-; CHECK: sth r3, 0(r4)
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: sth r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iness_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iness_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: sth r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
%conv3 = zext i1 %cmp to i16
@@ -77,13 +163,37 @@ entry:
define void @test_iness_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iness_sext_store:
-; CHECK: xor r3, r3, r4
-; CHECK: cntlzw r3, r3
-; CHECK: srwi r3, r3, 5
-; CHECK: xori r3, r3, 1
-; CHECK: neg r3, r3
-; CHECK: sth r3, 0(r4)
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: sth r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iness_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iness_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: sth r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
%conv3 = sext i1 %cmp to i16
@@ -93,11 +203,31 @@ entry:
define void @test_iness_z_store(i16 signext %a) {
; CHECK-LABEL: test_iness_z_store:
-; CHECK: cntlzw r3, r3
-; CHECK: srwi r3, r3, 5
-; CHECK: xori r3, r3, 1
-; CHECK: sth r3, 0(r4)
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: sth r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iness_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iness_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: sth r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%conv2 = zext i1 %cmp to i16
@@ -107,12 +237,34 @@ entry:
define void @test_iness_sext_z_store(i16 signext %a) {
; CHECK-LABEL: test_iness_sext_z_store:
-; CHECK: cntlzw r3, r3
-; CHECK: srwi r3, r3, 5
-; CHECK: xori r3, r3, 1
-; CHECK: neg r3, r3
-; CHECK: sth r3, 0(r4)
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: sth r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iness_sext_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iness_sext_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: sth r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%conv2 = sext i1 %cmp to i16
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesineuc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesineuc.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesineuc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesineuc.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i8 0, align 1
@@ -15,6 +15,21 @@ define signext i32 @test_ineuc(i8 zeroex
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ineuc:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ineuc:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
%conv2 = zext i1 %cmp to i32
@@ -30,6 +45,23 @@ define signext i32 @test_ineuc_sext(i8 z
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ineuc_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ineuc_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
%sub = sext i1 %cmp to i32
@@ -43,6 +75,19 @@ define signext i32 @test_ineuc_z(i8 zero
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ineuc_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ineuc_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%conv1 = zext i1 %cmp to i32
@@ -57,6 +102,21 @@ define signext i32 @test_ineuc_sext_z(i8
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ineuc_sext_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ineuc_sext_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%sub = sext i1 %cmp to i32
@@ -66,14 +126,33 @@ entry:
define void @test_ineuc_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_ineuc_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
-; CHECK-NEXT: stb r3, 0(r4)
+; CHECK-NEXT: stb r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ineuc_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: stb r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ineuc_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: stb r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
%conv3 = zext i1 %cmp to i8
@@ -85,14 +164,35 @@ define void @test_ineuc_sext_store(i8 ze
; CHECK-LABEL: test_ineuc_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
-; CHECK-NEXT: stb r3, 0(r4)
+; CHECK-NEXT: stb r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ineuc_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: stb r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ineuc_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: stb r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
%conv3 = sext i1 %cmp to i8
@@ -103,13 +203,30 @@ entry:
define void @test_ineuc_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_ineuc_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
-; CHECK-NEXT: stb r3, 0(r4)
+; CHECK-NEXT: stb r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ineuc_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: stb r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ineuc_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: stb r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%conv2 = zext i1 %cmp to i8
@@ -120,14 +237,33 @@ entry:
define void @test_ineuc_sext_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_ineuc_sext_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
-; CHECK-NEXT: stb r3, 0(r4)
+; CHECK-NEXT: stb r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ineuc_sext_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: stb r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ineuc_sext_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: stb r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%conv2 = sext i1 %cmp to i8
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesineui.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesineui.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesineui.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesineui.ll Tue Dec 4 12:14:57 2018
@@ -1,20 +1,36 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i32 0, align 4
define signext i32 @test_ineui(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_ineui:
-; CHECK: xor r3, r3, r4
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ineui:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ineui:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
%conv = zext i1 %cmp to i32
@@ -23,12 +39,30 @@ entry:
define signext i32 @test_ineui_sext(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_ineui_sext:
-; CHECK: xor r3, r3, r4
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ineui_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ineui_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
%sub = sext i1 %cmp to i32
@@ -37,10 +71,24 @@ entry:
define signext i32 @test_ineui_z(i32 zeroext %a) {
; CHECK-LABEL: test_ineui_z:
-; CHECK: cntlzw r3, r3
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ineui_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ineui_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%conv = zext i1 %cmp to i32
@@ -49,11 +97,27 @@ entry:
define signext i32 @test_ineui_sext_z(i32 zeroext %a) {
; CHECK-LABEL: test_ineui_sext_z:
-; CHECK: cntlzw r3, r3
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ineui_sext_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ineui_sext_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%sub = sext i1 %cmp to i32
@@ -62,12 +126,34 @@ entry:
define void @test_ineui_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_ineui_store:
-; CHECK: xor r3, r3, r4
-; CHECK: cntlzw r3, r3
-; CHECK: srwi r3, r3, 5
-; CHECK: xori r3, r3, 1
-; CHECK: stw r3, 0(r4)
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: stw r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ineui_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: stw r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ineui_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: stw r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
%conv = zext i1 %cmp to i32
@@ -77,13 +163,37 @@ entry:
define void @test_ineui_sext_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_ineui_sext_store:
-; CHECK: xor r3, r3, r4
-; CHECK: cntlzw r3, r3
-; CHECK: srwi r3, r3, 5
-; CHECK: xori r3, r3, 1
-; CHECK: neg r3, r3
-; CHECK: stw r3, 0(r4)
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: stw r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ineui_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: stw r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ineui_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: stw r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
%sub = sext i1 %cmp to i32
@@ -93,11 +203,31 @@ entry:
define void @test_ineui_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_ineui_z_store:
-; CHECK: cntlzw r3, r3
-; CHECK: srwi r3, r3, 5
-; CHECK: xori r3, r3, 1
-; CHECK: stw r3, 0(r4)
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: stw r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ineui_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: stw r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ineui_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: stw r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%conv = zext i1 %cmp to i32
@@ -107,12 +237,34 @@ entry:
define void @test_ineui_sext_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_ineui_sext_z_store:
-; CHECK: cntlzw r3, r3
-; CHECK: srwi r3, r3, 5
-; CHECK: xori r3, r3, 1
-; CHECK: neg r3, r3
-; CHECK: stw r3, 0(r4)
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: stw r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ineui_sext_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: stw r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ineui_sext_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: stw r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%sub = sext i1 %cmp to i32
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesineull.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesineull.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesineull.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesineull.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i64 0, align 8
@@ -15,6 +15,19 @@ define signext i32 @test_ineull(i64 %a,
; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ineull:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: addic r4, r3, -1
+; CHECK-BE-NEXT: subfe r3, r4, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ineull:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addic r4, r3, -1
+; CHECK-LE-NEXT: subfe r3, r4, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv = zext i1 %cmp to i32
@@ -28,6 +41,19 @@ define signext i32 @test_ineull_sext(i64
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ineull_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: subfic r3, r3, 0
+; CHECK-BE-NEXT: subfe r3, r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ineull_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: subfic r3, r3, 0
+; CHECK-LE-NEXT: subfe r3, r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%sub = sext i1 %cmp to i32
@@ -40,6 +66,17 @@ define signext i32 @test_ineull_z(i64 %a
; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ineull_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addic r4, r3, -1
+; CHECK-BE-NEXT: subfe r3, r4, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ineull_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: addic r4, r3, -1
+; CHECK-LE-NEXT: subfe r3, r4, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv = zext i1 %cmp to i32
@@ -52,6 +89,17 @@ define signext i32 @test_ineull_sext_z(i
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ineull_sext_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: subfic r3, r3, 0
+; CHECK-BE-NEXT: subfe r3, r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ineull_sext_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: subfic r3, r3, 0
+; CHECK-LE-NEXT: subfe r3, r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%sub = sext i1 %cmp to i32
@@ -61,13 +109,30 @@ entry:
define void @test_ineull_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_ineull_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
-; CHECK-NEXT: addic r5, r3, -1
-; CHECK-NEXT: subfe r3, r5, r3
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-NEXT: addic r4, r3, -1
+; CHECK-NEXT: subfe r3, r4, r3
+; CHECK-NEXT: std r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ineull_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: addic r5, r3, -1
+; CHECK-BE-NEXT: subfe r3, r5, r3
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ineull_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: addic r4, r3, -1
+; CHECK-LE-NEXT: subfe r3, r4, r3
+; CHECK-LE-NEXT: std r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = zext i1 %cmp to i64
@@ -78,13 +143,30 @@ entry:
define void @test_ineull_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_ineull_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ineull_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: subfic r3, r3, 0
+; CHECK-BE-NEXT: subfe r3, r3, r3
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ineull_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: subfic r3, r3, 0
+; CHECK-LE-NEXT: subfe r3, r3, r3
+; CHECK-LE-NEXT: std r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = sext i1 %cmp to i64
@@ -95,12 +177,27 @@ entry:
define void @test_ineull_z_store(i64 %a) {
; CHECK-LABEL: test_ineull_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: addic r5, r3, -1
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: subfe r3, r5, r3
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ineull_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: addic r5, r3, -1
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: subfe r3, r5, r3
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ineull_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: addic r5, r3, -1
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: subfe r3, r5, r3
+; CHECK-LE-NEXT: std r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = zext i1 %cmp to i64
@@ -111,12 +208,27 @@ entry:
define void @test_ineull_sext_z_store(i64 %a) {
; CHECK-LABEL: test_ineull_sext_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: subfic r3, r3, 0
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: subfe r3, r3, r3
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ineull_sext_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: subfic r3, r3, 0
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: subfe r3, r3, r3
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ineull_sext_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: subfic r3, r3, 0
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: subfe r3, r3, r3
+; CHECK-LE-NEXT: std r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = sext i1 %cmp to i64
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesineus.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesineus.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesineus.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesineus.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i16 0, align 2
@@ -16,6 +16,21 @@ define signext i32 @test_ineus(i16 zeroe
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ineus:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ineus:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
%conv2 = zext i1 %cmp to i32
@@ -31,6 +46,23 @@ define signext i32 @test_ineus_sext(i16
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ineus_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ineus_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
%sub = sext i1 %cmp to i32
@@ -44,6 +76,19 @@ define signext i32 @test_ineus_z(i16 zer
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ineus_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ineus_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%conv1 = zext i1 %cmp to i32
@@ -58,6 +103,21 @@ define signext i32 @test_ineus_sext_z(i1
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ineus_sext_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ineus_sext_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%sub = sext i1 %cmp to i32
@@ -67,14 +127,33 @@ entry:
define void @test_ineus_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_ineus_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
-; CHECK-NEXT: sth r3, 0(r4)
+; CHECK-NEXT: sth r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ineus_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ineus_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: sth r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
%conv3 = zext i1 %cmp to i16
@@ -86,14 +165,35 @@ define void @test_ineus_sext_store(i16 z
; CHECK-LABEL: test_ineus_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
-; CHECK-NEXT: sth r3, 0(r4)
+; CHECK-NEXT: sth r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ineus_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ineus_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: sth r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
%conv3 = sext i1 %cmp to i16
@@ -104,13 +204,30 @@ entry:
define void @test_ineus_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_ineus_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
-; CHECK-NEXT: sth r3, 0(r4)
+; CHECK-NEXT: sth r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ineus_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ineus_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: sth r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%conv2 = zext i1 %cmp to i16
@@ -121,14 +238,33 @@ entry:
define void @test_ineus_sext_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_ineus_sext_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
-; CHECK-NEXT: sth r3, 0(r4)
+; CHECK-NEXT: sth r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_ineus_sext_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_ineus_sext_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: sth r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%conv2 = sext i1 %cmp to i16
Modified: llvm/trunk/test/CodeGen/PowerPC/testCompareslleqsc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testCompareslleqsc.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testCompareslleqsc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testCompareslleqsc.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; ModuleID = 'ComparisonTestCases/testCompareslleqsc.c'
@@ -17,6 +17,19 @@ define i64 @test_lleqsc(i8 signext %a, i
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lleqsc:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lleqsc:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%conv3 = zext i1 %cmp to i64
@@ -32,6 +45,21 @@ define i64 @test_lleqsc_sext(i8 signext
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lleqsc_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lleqsc_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%conv3 = sext i1 %cmp to i64
@@ -45,6 +73,17 @@ define i64 @test_lleqsc_z(i8 signext %a)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lleqsc_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lleqsc_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv2 = zext i1 %cmp to i64
@@ -59,6 +98,19 @@ define i64 @test_lleqsc_sext_z(i8 signex
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lleqsc_sext_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lleqsc_sext_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv2 = sext i1 %cmp to i64
@@ -69,13 +121,30 @@ entry:
define void @test_lleqsc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lleqsc_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: stb r3, 0(r4)
+; CHECK-NEXT: stb r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lleqsc_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: stb r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lleqsc_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: stb r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%conv3 = zext i1 %cmp to i8
@@ -87,14 +156,33 @@ entry:
define void @test_lleqsc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lleqsc_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
-; CHECK-NEXT: stb r3, 0(r4)
+; CHECK-NEXT: stb r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lleqsc_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: stb r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lleqsc_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: stb r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%conv3 = sext i1 %cmp to i8
@@ -106,12 +194,27 @@ entry:
define void @test_lleqsc_z_store(i8 signext %a) {
; CHECK-LABEL: test_lleqsc_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: stb r3, 0(r4)
+; CHECK-NEXT: stb r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lleqsc_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: stb r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lleqsc_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: stb r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv2 = zext i1 %cmp to i8
@@ -123,13 +226,30 @@ entry:
define void @test_lleqsc_sext_z_store(i8 signext %a) {
; CHECK-LABEL: test_lleqsc_sext_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
-; CHECK-NEXT: stb r3, 0(r4)
+; CHECK-NEXT: stb r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lleqsc_sext_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: stb r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lleqsc_sext_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: stb r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv2 = sext i1 %cmp to i8
Modified: llvm/trunk/test/CodeGen/PowerPC/testCompareslleqsi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testCompareslleqsi.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testCompareslleqsi.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testCompareslleqsi.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i32 0, align 4
@@ -16,6 +16,19 @@ define i64 @test_lleqsi(i32 signext %a,
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lleqsi:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lleqsi:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%conv1 = zext i1 %cmp to i64
@@ -31,6 +44,21 @@ define i64 @test_lleqsi_sext(i32 signext
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lleqsi_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lleqsi_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%conv1 = sext i1 %cmp to i64
@@ -44,6 +72,17 @@ define i64 @test_lleqsi_z(i32 signext %a
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lleqsi_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lleqsi_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%conv1 = zext i1 %cmp to i64
@@ -58,6 +97,19 @@ define i64 @test_lleqsi_sext_z(i32 signe
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lleqsi_sext_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lleqsi_sext_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%conv1 = sext i1 %cmp to i64
@@ -68,13 +120,30 @@ entry:
define void @test_lleqsi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lleqsi_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: stw r3, 0(r4)
+; CHECK-NEXT: stw r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lleqsi_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: stw r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lleqsi_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: stw r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%conv = zext i1 %cmp to i32
@@ -86,14 +155,33 @@ entry:
define void @test_lleqsi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lleqsi_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
-; CHECK-NEXT: stw r3, 0(r4)
+; CHECK-NEXT: stw r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lleqsi_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: stw r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lleqsi_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: stw r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%sub = sext i1 %cmp to i32
@@ -105,13 +193,28 @@ entry:
define void @test_lleqsi_z_store(i32 signext %a) {
; CHECK-LABEL: test_lleqsi_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: stw r3, 0(r4)
+; CHECK-NEXT: stw r3, glob at toc@l(r4)
; CHECK-NEXT: blr
; CHECKNEXT: blr
+; CHECK-BE-LABEL: test_lleqsi_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: stw r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lleqsi_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: stw r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%conv = zext i1 %cmp to i32
@@ -123,13 +226,30 @@ entry:
define void @test_lleqsi_sext_z_store(i32 signext %a) {
; CHECK-LABEL: test_lleqsi_sext_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
-; CHECK-NEXT: stw r3, 0(r4)
+; CHECK-NEXT: stw r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lleqsi_sext_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: stw r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lleqsi_sext_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: stw r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%sub = sext i1 %cmp to i32
Modified: llvm/trunk/test/CodeGen/PowerPC/testCompareslleqsll.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testCompareslleqsll.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testCompareslleqsll.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testCompareslleqsll.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i64 0, align 8
@@ -16,6 +16,19 @@ define i64 @test_lleqsll(i64 %a, i64 %b)
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lleqsll:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzd r3, r3
+; CHECK-BE-NEXT: rldicl r3, r3, 58, 63
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lleqsll:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzd r3, r3
+; CHECK-LE-NEXT: rldicl r3, r3, 58, 63
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%conv1 = zext i1 %cmp to i64
@@ -30,6 +43,19 @@ define i64 @test_lleqsll_sext(i64 %a, i6
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lleqsll_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: addic r3, r3, -1
+; CHECK-BE-NEXT: subfe r3, r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lleqsll_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addic r3, r3, -1
+; CHECK-LE-NEXT: subfe r3, r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%conv1 = sext i1 %cmp to i64
@@ -43,6 +69,17 @@ define i64 @test_lleqsll_z(i64 %a) {
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lleqsll_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzd r3, r3
+; CHECK-BE-NEXT: rldicl r3, r3, 58, 63
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lleqsll_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzd r3, r3
+; CHECK-LE-NEXT: rldicl r3, r3, 58, 63
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%conv1 = zext i1 %cmp to i64
@@ -56,6 +93,17 @@ define i64 @test_lleqsll_sext_z(i64 %a)
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lleqsll_sext_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addic r3, r3, -1
+; CHECK-BE-NEXT: subfe r3, r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lleqsll_sext_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: addic r3, r3, -1
+; CHECK-LE-NEXT: subfe r3, r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%conv1 = sext i1 %cmp to i64
@@ -66,13 +114,30 @@ entry:
define void @test_lleqsll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_lleqsll_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lleqsll_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: cntlzd r3, r3
+; CHECK-BE-NEXT: rldicl r3, r3, 58, 63
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lleqsll_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzd r3, r3
+; CHECK-LE-NEXT: rldicl r3, r3, 58, 63
+; CHECK-LE-NEXT: std r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%conv1 = zext i1 %cmp to i64
@@ -84,13 +149,30 @@ entry:
define void @test_lleqsll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_lleqsll_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lleqsll_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: addic r3, r3, -1
+; CHECK-BE-NEXT: subfe r3, r3, r3
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lleqsll_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: addic r3, r3, -1
+; CHECK-LE-NEXT: subfe r3, r3, r3
+; CHECK-LE-NEXT: std r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%conv1 = sext i1 %cmp to i64
@@ -102,12 +184,27 @@ entry:
define void @test_lleqsll_z_store(i64 %a) {
; CHECK-LABEL: test_lleqsll_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: cntlzd r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 58, 63
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lleqsll_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzd r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: rldicl r3, r3, 58, 63
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lleqsll_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzd r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: rldicl r3, r3, 58, 63
+; CHECK-LE-NEXT: std r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%conv1 = zext i1 %cmp to i64
@@ -119,12 +216,27 @@ entry:
define void @test_lleqsll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_lleqsll_sext_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: addic r3, r3, -1
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: subfe r3, r3, r3
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lleqsll_sext_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: addic r3, r3, -1
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: subfe r3, r3, r3
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lleqsll_sext_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: addic r3, r3, -1
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: subfe r3, r3, r3
+; CHECK-LE-NEXT: std r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%conv1 = sext i1 %cmp to i64
Modified: llvm/trunk/test/CodeGen/PowerPC/testCompareslleqss.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testCompareslleqss.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testCompareslleqss.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testCompareslleqss.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i16 0, align 2
@@ -16,6 +16,19 @@ define i64 @test_lleqss(i16 signext %a,
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lleqss:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lleqss:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%conv3 = zext i1 %cmp to i64
@@ -31,6 +44,21 @@ define i64 @test_lleqss_sext(i16 signext
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lleqss_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lleqss_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%conv3 = sext i1 %cmp to i64
@@ -44,6 +72,17 @@ define i64 @test_lleqss_z(i16 signext %a
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lleqss_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lleqss_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%conv2 = zext i1 %cmp to i64
@@ -58,6 +97,19 @@ define i64 @test_lleqss_sext_z(i16 signe
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lleqss_sext_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lleqss_sext_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%conv2 = sext i1 %cmp to i64
@@ -68,13 +120,30 @@ entry:
define void @test_lleqss_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_lleqss_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: sth r3, 0(r4)
+; CHECK-NEXT: sth r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lleqss_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lleqss_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: sth r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%conv3 = zext i1 %cmp to i16
@@ -86,14 +155,33 @@ entry:
define void @test_lleqss_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_lleqss_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
-; CHECK-NEXT: sth r3, 0(r4)
+; CHECK-NEXT: sth r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lleqss_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lleqss_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: sth r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%conv3 = sext i1 %cmp to i16
@@ -105,12 +193,27 @@ entry:
define void @test_lleqss_z_store(i16 signext %a) {
; CHECK-LABEL: test_lleqss_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: sth r3, 0(r4)
+; CHECK-NEXT: sth r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lleqss_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lleqss_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: sth r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%conv2 = zext i1 %cmp to i16
@@ -122,13 +225,30 @@ entry:
define void @test_lleqss_sext_z_store(i16 signext %a) {
; CHECK-LABEL: test_lleqss_sext_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
-; CHECK-NEXT: sth r3, 0(r4)
+; CHECK-NEXT: sth r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lleqss_sext_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lleqss_sext_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: sth r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%conv2 = sext i1 %cmp to i16
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllequc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllequc.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllequc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllequc.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i8 0, align 1
@@ -16,6 +16,19 @@ define i64 @test_llequc(i8 zeroext %a, i
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llequc:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llequc:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%conv3 = zext i1 %cmp to i64
@@ -31,6 +44,21 @@ define i64 @test_llequc_sext(i8 zeroext
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llequc_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llequc_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%conv3 = sext i1 %cmp to i64
@@ -44,6 +72,17 @@ define i64 @test_llequc_z(i8 zeroext %a)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llequc_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llequc_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv2 = zext i1 %cmp to i64
@@ -58,6 +97,19 @@ define i64 @test_llequc_sext_z(i8 zeroex
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llequc_sext_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llequc_sext_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv2 = sext i1 %cmp to i64
@@ -68,13 +120,30 @@ entry:
define void @test_llequc_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llequc_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: stb r3, 0(r4)
+; CHECK-NEXT: stb r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llequc_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: stb r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llequc_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: stb r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%conv3 = zext i1 %cmp to i8
@@ -86,14 +155,33 @@ entry:
define void @test_llequc_sext_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llequc_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
-; CHECK-NEXT: stb r3, 0(r4)
+; CHECK-NEXT: stb r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llequc_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: stb r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llequc_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: stb r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%conv3 = sext i1 %cmp to i8
@@ -105,12 +193,27 @@ entry:
define void @test_llequc_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_llequc_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: stb r3, 0(r4)
+; CHECK-NEXT: stb r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llequc_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: stb r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llequc_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: stb r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv2 = zext i1 %cmp to i8
@@ -122,13 +225,30 @@ entry:
define void @test_llequc_sext_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_llequc_sext_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
-; CHECK-NEXT: stb r3, 0(r4)
+; CHECK-NEXT: stb r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llequc_sext_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: stb r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llequc_sext_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: stb r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv2 = sext i1 %cmp to i8
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllequi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllequi.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllequi.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllequi.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i32 0, align 4
@@ -16,6 +16,19 @@ define i64 @test_llequi(i32 zeroext %a,
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llequi:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llequi:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%conv1 = zext i1 %cmp to i64
@@ -31,6 +44,21 @@ define i64 @test_llequi_sext(i32 zeroext
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llequi_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llequi_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%conv1 = sext i1 %cmp to i64
@@ -44,6 +72,17 @@ define i64 @test_llequi_z(i32 zeroext %a
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llequi_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llequi_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%conv1 = zext i1 %cmp to i64
@@ -58,6 +97,19 @@ define i64 @test_llequi_sext_z(i32 zeroe
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llequi_sext_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llequi_sext_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%conv1 = sext i1 %cmp to i64
@@ -68,13 +120,30 @@ entry:
define void @test_llequi_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llequi_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: stw r3, 0(r4)
+; CHECK-NEXT: stw r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llequi_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: stw r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llequi_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: stw r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%conv = zext i1 %cmp to i32
@@ -86,14 +155,33 @@ entry:
define void @test_llequi_sext_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llequi_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
-; CHECK-NEXT: stw r3, 0(r4)
+; CHECK-NEXT: stw r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llequi_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: stw r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llequi_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: stw r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%sub = sext i1 %cmp to i32
@@ -105,12 +193,27 @@ entry:
define void @test_llequi_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_llequi_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: stw r3, 0(r4)
+; CHECK-NEXT: stw r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llequi_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: stw r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llequi_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: stw r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%conv = zext i1 %cmp to i32
@@ -122,13 +225,30 @@ entry:
define void @test_llequi_sext_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_llequi_sext_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
-; CHECK-NEXT: stw r3, 0(r4)
+; CHECK-NEXT: stw r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llequi_sext_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: stw r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llequi_sext_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: stw r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%sub = sext i1 %cmp to i32
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllequll.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllequll.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllequll.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllequll.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i64 0, align 8
@@ -16,6 +16,19 @@ define i64 @test_llequll(i64 %a, i64 %b)
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llequll:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzd r3, r3
+; CHECK-BE-NEXT: rldicl r3, r3, 58, 63
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llequll:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzd r3, r3
+; CHECK-LE-NEXT: rldicl r3, r3, 58, 63
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%conv1 = zext i1 %cmp to i64
@@ -30,6 +43,19 @@ define i64 @test_llequll_sext(i64 %a, i6
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llequll_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: addic r3, r3, -1
+; CHECK-BE-NEXT: subfe r3, r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llequll_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addic r3, r3, -1
+; CHECK-LE-NEXT: subfe r3, r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%conv1 = sext i1 %cmp to i64
@@ -43,6 +69,17 @@ define i64 @test_llequll_z(i64 %a) {
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llequll_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzd r3, r3
+; CHECK-BE-NEXT: rldicl r3, r3, 58, 63
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llequll_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzd r3, r3
+; CHECK-LE-NEXT: rldicl r3, r3, 58, 63
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%conv1 = zext i1 %cmp to i64
@@ -56,6 +93,17 @@ define i64 @test_llequll_sext_z(i64 %a)
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llequll_sext_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addic r3, r3, -1
+; CHECK-BE-NEXT: subfe r3, r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llequll_sext_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: addic r3, r3, -1
+; CHECK-LE-NEXT: subfe r3, r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%conv1 = sext i1 %cmp to i64
@@ -66,13 +114,30 @@ entry:
define void @test_llequll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llequll_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llequll_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: cntlzd r3, r3
+; CHECK-BE-NEXT: rldicl r3, r3, 58, 63
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llequll_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzd r3, r3
+; CHECK-LE-NEXT: rldicl r3, r3, 58, 63
+; CHECK-LE-NEXT: std r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%conv1 = zext i1 %cmp to i64
@@ -84,13 +149,30 @@ entry:
define void @test_llequll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llequll_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llequll_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: addic r3, r3, -1
+; CHECK-BE-NEXT: subfe r3, r3, r3
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llequll_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: addic r3, r3, -1
+; CHECK-LE-NEXT: subfe r3, r3, r3
+; CHECK-LE-NEXT: std r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%conv1 = sext i1 %cmp to i64
@@ -102,12 +184,27 @@ entry:
define void @test_llequll_z_store(i64 %a) {
; CHECK-LABEL: test_llequll_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: cntlzd r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 58, 63
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llequll_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzd r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: rldicl r3, r3, 58, 63
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llequll_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzd r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: rldicl r3, r3, 58, 63
+; CHECK-LE-NEXT: std r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%conv1 = zext i1 %cmp to i64
@@ -119,12 +216,27 @@ entry:
define void @test_llequll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_llequll_sext_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: addic r3, r3, -1
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: subfe r3, r3, r3
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llequll_sext_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: addic r3, r3, -1
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: subfe r3, r3, r3
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llequll_sext_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: addic r3, r3, -1
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: subfe r3, r3, r3
+; CHECK-LE-NEXT: std r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%conv1 = sext i1 %cmp to i64
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllequs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllequs.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllequs.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllequs.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i16 0, align 2
@@ -16,6 +16,19 @@ define i64 @test_llequs(i16 zeroext %a,
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llequs:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llequs:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%conv3 = zext i1 %cmp to i64
@@ -31,6 +44,21 @@ define i64 @test_llequs_sext(i16 zeroext
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llequs_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llequs_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%conv3 = sext i1 %cmp to i64
@@ -44,6 +72,17 @@ define i64 @test_llequs_z(i16 zeroext %a
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llequs_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llequs_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%conv2 = zext i1 %cmp to i64
@@ -58,6 +97,19 @@ define i64 @test_llequs_sext_z(i16 zeroe
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llequs_sext_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llequs_sext_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%conv2 = sext i1 %cmp to i64
@@ -68,13 +120,30 @@ entry:
define void @test_llequs_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llequs_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: sth r3, 0(r4)
+; CHECK-NEXT: sth r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llequs_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llequs_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: sth r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%conv3 = zext i1 %cmp to i16
@@ -86,14 +155,33 @@ entry:
define void @test_llequs_sext_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llequs_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
-; CHECK-NEXT: sth r3, 0(r4)
+; CHECK-NEXT: sth r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llequs_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llequs_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: sth r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%conv3 = sext i1 %cmp to i16
@@ -105,12 +193,27 @@ entry:
define void @test_llequs_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_llequs_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: sth r3, 0(r4)
+; CHECK-NEXT: sth r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llequs_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llequs_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: sth r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%conv2 = zext i1 %cmp to i16
@@ -122,13 +225,30 @@ entry:
define void @test_llequs_sext_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_llequs_sext_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
-; CHECK-NEXT: sth r3, 0(r4)
+; CHECK-NEXT: sth r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llequs_sext_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llequs_sext_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: sth r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%conv2 = sext i1 %cmp to i16
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllgesc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgesc.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllgesc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllgesc.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i8 0, align 1
@@ -14,6 +14,19 @@ define i64 @test_llgesc(i8 signext %a, i
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llgesc:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sub r3, r3, r4
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llgesc:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r3, r4
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
%conv3 = zext i1 %cmp to i64
@@ -27,6 +40,19 @@ define i64 @test_llgesc_sext(i8 signext
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llgesc_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sub r3, r3, r4
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: addi r3, r3, -1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llgesc_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r3, r4
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: addi r3, r3, -1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
%conv3 = sext i1 %cmp to i64
@@ -36,13 +62,30 @@ entry:
define void @test_llgesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_llgesc_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
-; CHECK-NEXT: stb r3, 0(r4)
+; CHECK-NEXT: stb r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llgesc_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: sub r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: stb r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llgesc_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: stb r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
%conv3 = zext i1 %cmp to i8
@@ -53,13 +96,30 @@ entry:
define void @test_llgesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_llgesc_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
-; CHECK-NEXT: stb r3, 0(r4)
+; CHECK-NEXT: stb r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llgesc_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: sub r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: addi r3, r3, -1
+; CHECK-BE-NEXT: stb r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llgesc_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: addi r3, r3, -1
+; CHECK-LE-NEXT: stb r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
%conv3 = sext i1 %cmp to i8
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllgesi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgesi.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllgesi.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllgesi.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i32 0, align 4
@@ -14,6 +14,19 @@ define i64 @test_llgesi(i32 signext %a,
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llgesi:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sub r3, r3, r4
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llgesi:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r3, r4
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%conv1 = zext i1 %cmp to i64
@@ -27,6 +40,19 @@ define i64 @test_llgesi_sext(i32 signext
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llgesi_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sub r3, r3, r4
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: addi r3, r3, -1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llgesi_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r3, r4
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: addi r3, r3, -1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%conv1 = sext i1 %cmp to i64
@@ -36,13 +62,30 @@ entry:
define void @test_llgesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_llgesi_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
-; CHECK-NEXT: stw r3, 0(r4)
+; CHECK-NEXT: stw r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llgesi_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: sub r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: stw r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llgesi_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: stw r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%conv = zext i1 %cmp to i32
@@ -53,13 +96,30 @@ entry:
define void @test_llgesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_llgesi_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
-; CHECK-NEXT: stw r3, 0(r4)
+; CHECK-NEXT: stw r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llgesi_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: sub r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: addi r3, r3, -1
+; CHECK-BE-NEXT: stw r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llgesi_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: addi r3, r3, -1
+; CHECK-LE-NEXT: stw r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%sub = sext i1 %cmp to i32
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllgesll.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgesll.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllgesll.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllgesll.ll Tue Dec 4 12:14:57 2018
@@ -1,10 +1,10 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i64 0, align 8
define i64 @test_llgesll(i64 %a, i64 %b) {
@@ -15,6 +15,21 @@ define i64 @test_llgesll(i64 %a, i64 %b)
; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llgesll:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sradi r5, r3, 63
+; CHECK-BE-NEXT: rldicl r6, r4, 1, 63
+; CHECK-BE-NEXT: subfc r3, r4, r3
+; CHECK-BE-NEXT: adde r3, r5, r6
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llgesll:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sradi r5, r3, 63
+; CHECK-LE-NEXT: rldicl r6, r4, 1, 63
+; CHECK-LE-NEXT: subfc r3, r4, r3
+; CHECK-LE-NEXT: adde r3, r5, r6
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i64 %a, %b
%conv1 = zext i1 %cmp to i64
@@ -30,6 +45,23 @@ define i64 @test_llgesll_sext(i64 %a, i6
; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llgesll_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sradi r5, r3, 63
+; CHECK-BE-NEXT: rldicl r6, r4, 1, 63
+; CHECK-BE-NEXT: subfc r3, r4, r3
+; CHECK-BE-NEXT: adde r3, r5, r6
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llgesll_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sradi r5, r3, 63
+; CHECK-LE-NEXT: rldicl r6, r4, 1, 63
+; CHECK-LE-NEXT: subfc r3, r4, r3
+; CHECK-LE-NEXT: adde r3, r5, r6
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i64 %a, %b
%conv1 = sext i1 %cmp to i64
@@ -42,6 +74,17 @@ define i64 @test_llgesll_z(i64 %a) {
; CHECK-NEXT: not r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llgesll_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: not r3, r3
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llgesll_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: not r3, r3
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, -1
%conv1 = zext i1 %cmp to i64
@@ -54,6 +97,17 @@ define i64 @test_llgesll_sext_z(i64 %a)
; CHECK-NEXT: not r3, r3
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llgesll_sext_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: not r3, r3
+; CHECK-BE-NEXT: sradi r3, r3, 63
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llgesll_sext_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: not r3, r3
+; CHECK-LE-NEXT: sradi r3, r3, 63
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, -1
%conv1 = sext i1 %cmp to i64
@@ -63,12 +117,33 @@ entry:
define void @test_llgesll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgesll_store:
; CHECK: # %bb.0: # %entry
-; CHECK: sradi r6, r3, 63
-; CHECK: subfc r3, r4, r3
-; CHECK: rldicl r3, r4, 1, 63
-; CHECK: adde r3, r6, r3
-; CHECK: std r3,
+; CHECK-NEXT: sradi r6, r3, 63
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-NEXT: subfc r3, r4, r3
+; CHECK-NEXT: rldicl r3, r4, 1, 63
+; CHECK-NEXT: adde r3, r6, r3
+; CHECK-NEXT: std r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llgesll_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: sradi r6, r3, 63
+; CHECK-BE-NEXT: ld r5, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: subfc r3, r4, r3
+; CHECK-BE-NEXT: rldicl r3, r4, 1, 63
+; CHECK-BE-NEXT: adde r3, r6, r3
+; CHECK-BE-NEXT: std r3, 0(r5)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llgesll_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sradi r6, r3, 63
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: subfc r3, r4, r3
+; CHECK-LE-NEXT: rldicl r3, r4, 1, 63
+; CHECK-LE-NEXT: adde r3, r6, r3
+; CHECK-LE-NEXT: std r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i64 %a, %b
%conv1 = zext i1 %cmp to i64
@@ -80,14 +155,35 @@ define void @test_llgesll_sext_store(i64
; CHECK-LABEL: test_llgesll_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r6, r3, 63
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: rldicl r3, r4, 1, 63
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: adde r3, r6, r3
; CHECK-NEXT: neg r3, r3
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llgesll_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sradi r6, r3, 63
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: subfc r3, r4, r3
+; CHECK-BE-NEXT: rldicl r3, r4, 1, 63
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: adde r3, r6, r3
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llgesll_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sradi r6, r3, 63
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: subfc r3, r4, r3
+; CHECK-LE-NEXT: rldicl r3, r4, 1, 63
+; CHECK-LE-NEXT: adde r3, r6, r3
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: std r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i64 %a, %b
%conv1 = sext i1 %cmp to i64
@@ -98,12 +194,27 @@ entry:
define void @test_llgesll_z_store(i64 %a) {
; CHECK-LABEL: test_llgesll_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: not r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llgesll_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: not r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llgesll_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: not r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: std r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, -1
%conv1 = zext i1 %cmp to i64
@@ -114,12 +225,27 @@ entry:
define void @test_llgesll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_llgesll_sext_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: not r3, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: sradi r3, r3, 63
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llgesll_sext_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: not r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: sradi r3, r3, 63
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llgesll_sext_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: not r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: sradi r3, r3, 63
+; CHECK-LE-NEXT: std r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, -1
%conv1 = sext i1 %cmp to i64
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllgess.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgess.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllgess.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllgess.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i16 0, align 2
@@ -14,6 +14,19 @@ define i64 @test_llgess(i16 signext %a,
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llgess:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sub r3, r3, r4
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llgess:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r3, r4
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
%conv3 = zext i1 %cmp to i64
@@ -27,6 +40,19 @@ define i64 @test_llgess_sext(i16 signext
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llgess_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sub r3, r3, r4
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: addi r3, r3, -1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llgess_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r3, r4
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: addi r3, r3, -1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
%conv3 = sext i1 %cmp to i64
@@ -36,13 +62,30 @@ entry:
define void @test_llgess_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llgess_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
-; CHECK-NEXT: sth r3, 0(r4)
+; CHECK-NEXT: sth r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llgess_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: sub r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llgess_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: sth r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
%conv3 = zext i1 %cmp to i16
@@ -53,13 +96,30 @@ entry:
define void @test_llgess_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llgess_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
-; CHECK-NEXT: sth r3, 0(r4)
+; CHECK-NEXT: sth r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llgess_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: sub r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: addi r3, r3, -1
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llgess_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: addi r3, r3, -1
+; CHECK-LE-NEXT: sth r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
%conv3 = sext i1 %cmp to i16
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllgtsll.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgtsll.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllgtsll.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllgtsll.ll Tue Dec 4 12:14:57 2018
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllgtuc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgtuc.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllgtuc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllgtuc.ll Tue Dec 4 12:14:57 2018
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllgtui.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgtui.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllgtui.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllgtui.ll Tue Dec 4 12:14:57 2018
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllgtus.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgtus.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllgtus.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllgtus.ll Tue Dec 4 12:14:57 2018
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
Modified: llvm/trunk/test/CodeGen/PowerPC/testCompareslllesc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testCompareslllesc.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testCompareslllesc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testCompareslllesc.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i8 0, align 1
@@ -15,6 +15,19 @@ define i64 @test_lllesc(i8 signext %a, i
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lllesc:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sub r3, r4, r3
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lllesc:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r4, r3
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
%conv3 = zext i1 %cmp to i64
@@ -28,6 +41,19 @@ define i64 @test_lllesc_sext(i8 signext
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lllesc_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sub r3, r4, r3
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: addi r3, r3, -1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lllesc_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r4, r3
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: addi r3, r3, -1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
%conv3 = sext i1 %cmp to i64
@@ -37,13 +63,30 @@ entry:
define void @test_lllesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lllesc_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r4, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
-; CHECK-NEXT: stb r3, 0(r4)
+; CHECK-NEXT: stb r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lllesc_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: sub r3, r4, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: stb r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lllesc_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r4, r3
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: stb r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
%conv3 = zext i1 %cmp to i8
@@ -54,13 +97,30 @@ entry:
define void @test_lllesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lllesc_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r4, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
-; CHECK-NEXT: stb r3, 0(r4)
+; CHECK-NEXT: stb r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lllesc_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: sub r3, r4, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: addi r3, r3, -1
+; CHECK-BE-NEXT: stb r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lllesc_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r4, r3
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: addi r3, r3, -1
+; CHECK-LE-NEXT: stb r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
%conv3 = sext i1 %cmp to i8
Modified: llvm/trunk/test/CodeGen/PowerPC/testCompareslllesi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testCompareslllesi.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testCompareslllesi.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testCompareslllesi.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i32 0, align 4
@@ -15,6 +15,19 @@ define i64 @test_lllesi(i32 signext %a,
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lllesi:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sub r3, r4, r3
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lllesi:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r4, r3
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
%conv1 = zext i1 %cmp to i64
@@ -28,6 +41,19 @@ define i64 @test_lllesi_sext(i32 signext
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lllesi_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sub r3, r4, r3
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: addi r3, r3, -1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lllesi_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r4, r3
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: addi r3, r3, -1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
%conv1 = sext i1 %cmp to i64
@@ -37,13 +63,30 @@ entry:
define void @test_lllesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lllesi_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r4, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
-; CHECK-NEXT: stw r3, 0(r4)
+; CHECK-NEXT: stw r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lllesi_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: sub r3, r4, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: stw r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lllesi_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r4, r3
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: stw r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
%conv = zext i1 %cmp to i32
@@ -54,13 +97,30 @@ entry:
define void @test_lllesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lllesi_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r4, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
-; CHECK-NEXT: stw r3, 0(r4)
+; CHECK-NEXT: stw r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lllesi_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: sub r3, r4, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: addi r3, r3, -1
+; CHECK-BE-NEXT: stw r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lllesi_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r4, r3
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: addi r3, r3, -1
+; CHECK-LE-NEXT: stw r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
%sub = sext i1 %cmp to i32
Modified: llvm/trunk/test/CodeGen/PowerPC/testCompareslllesll.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testCompareslllesll.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testCompareslllesll.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testCompareslllesll.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i64 0, align 8
@@ -16,6 +16,21 @@ define i64 @test_lllesll(i64 %a, i64 %b)
; CHECK-NEXT: subfc r3, r3, r4
; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lllesll:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sradi r5, r4, 63
+; CHECK-BE-NEXT: rldicl r6, r3, 1, 63
+; CHECK-BE-NEXT: subfc r3, r3, r4
+; CHECK-BE-NEXT: adde r3, r5, r6
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lllesll:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sradi r5, r4, 63
+; CHECK-LE-NEXT: rldicl r6, r3, 1, 63
+; CHECK-LE-NEXT: subfc r3, r3, r4
+; CHECK-LE-NEXT: adde r3, r5, r6
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sle i64 %a, %b
%conv1 = zext i1 %cmp to i64
@@ -32,6 +47,23 @@ define i64 @test_lllesll_sext(i64 %a, i6
; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lllesll_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sradi r5, r4, 63
+; CHECK-BE-NEXT: rldicl r6, r3, 1, 63
+; CHECK-BE-NEXT: subfc r3, r3, r4
+; CHECK-BE-NEXT: adde r3, r5, r6
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lllesll_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sradi r5, r4, 63
+; CHECK-LE-NEXT: rldicl r6, r3, 1, 63
+; CHECK-LE-NEXT: subfc r3, r3, r4
+; CHECK-LE-NEXT: adde r3, r5, r6
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sle i64 %a, %b
%conv1 = sext i1 %cmp to i64
@@ -46,6 +78,19 @@ define i64 @test_lllesll_z(i64 %a) {
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lllesll_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addi r4, r3, -1
+; CHECK-BE-NEXT: or r3, r4, r3
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lllesll_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: addi r4, r3, -1
+; CHECK-LE-NEXT: or r3, r4, r3
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp slt i64 %a, 1
%conv1 = zext i1 %cmp to i64
@@ -60,6 +105,19 @@ define i64 @test_lllesll_sext_z(i64 %a)
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lllesll_sext_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addi r4, r3, -1
+; CHECK-BE-NEXT: or r3, r4, r3
+; CHECK-BE-NEXT: sradi r3, r3, 63
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lllesll_sext_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: addi r4, r3, -1
+; CHECK-LE-NEXT: or r3, r4, r3
+; CHECK-LE-NEXT: sradi r3, r3, 63
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp slt i64 %a, 1
%conv1 = sext i1 %cmp to i64
@@ -70,14 +128,33 @@ entry:
define void @test_lllesll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_lllesll_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sradi r6, r4, 63
-; CHECK-NEXT: ld r5, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: subfc r4, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: adde r3, r6, r3
-; CHECK-NEXT: std r3, 0(r5)
+; CHECK-NEXT: std r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lllesll_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: sradi r6, r4, 63
+; CHECK-BE-NEXT: ld r5, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: subfc r4, r3, r4
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: adde r3, r6, r3
+; CHECK-BE-NEXT: std r3, 0(r5)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lllesll_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sradi r6, r4, 63
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: subfc r4, r3, r4
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: adde r3, r6, r3
+; CHECK-LE-NEXT: std r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sle i64 %a, %b
%conv1 = zext i1 %cmp to i64
@@ -90,14 +167,35 @@ define void @test_lllesll_sext_store(i64
; CHECK-LABEL: test_lllesll_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r6, r4, 63
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: subfc r4, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: adde r3, r6, r3
; CHECK-NEXT: neg r3, r3
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lllesll_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sradi r6, r4, 63
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: subfc r4, r3, r4
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: adde r3, r6, r3
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lllesll_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sradi r6, r4, 63
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: subfc r4, r3, r4
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: adde r3, r6, r3
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: std r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sle i64 %a, %b
%conv1 = sext i1 %cmp to i64
@@ -109,13 +207,30 @@ entry:
define void @test_lllesll_z_store(i64 %a) {
; CHECK-LABEL: test_lllesll_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: addi r5, r3, -1
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: or r3, r5, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lllesll_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: addi r5, r3, -1
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: or r3, r5, r3
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lllesll_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: addi r5, r3, -1
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: or r3, r5, r3
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: std r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp slt i64 %a, 1
%conv1 = zext i1 %cmp to i64
@@ -127,13 +242,30 @@ entry:
define void @test_lllesll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_lllesll_sext_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: addi r5, r3, -1
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: or r3, r5, r3
; CHECK-NEXT: sradi r3, r3, 63
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_lllesll_sext_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: addi r5, r3, -1
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: or r3, r5, r3
+; CHECK-BE-NEXT: sradi r3, r3, 63
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_lllesll_sext_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: addi r5, r3, -1
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: or r3, r5, r3
+; CHECK-LE-NEXT: sradi r3, r3, 63
+; CHECK-LE-NEXT: std r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp slt i64 %a, 1
%conv1 = sext i1 %cmp to i64
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllless.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllless.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllless.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllless.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i16 0, align 2
@@ -15,6 +15,19 @@ define i64 @test_llless(i16 signext %a,
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llless:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sub r3, r4, r3
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llless:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r4, r3
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
%conv3 = zext i1 %cmp to i64
@@ -28,6 +41,19 @@ define i64 @test_llless_sext(i16 signext
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llless_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: sub r3, r4, r3
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: addi r3, r3, -1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llless_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r4, r3
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: addi r3, r3, -1
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
%conv3 = sext i1 %cmp to i64
@@ -37,13 +63,30 @@ entry:
define void @test_llless_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llless_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r4, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
-; CHECK-NEXT: sth r3, 0(r4)
+; CHECK-NEXT: sth r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llless_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: sub r3, r4, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: xori r3, r3, 1
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llless_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r4, r3
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: xori r3, r3, 1
+; CHECK-LE-NEXT: sth r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
%conv3 = zext i1 %cmp to i16
@@ -54,13 +97,30 @@ entry:
define void @test_llless_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llless_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r4, r3
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
-; CHECK-NEXT: sth r3, 0(r4)
+; CHECK-NEXT: sth r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llless_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: sub r3, r4, r3
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT: addi r3, r3, -1
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llless_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: sub r3, r4, r3
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT: addi r3, r3, -1
+; CHECK-LE-NEXT: sth r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
%conv3 = sext i1 %cmp to i16
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllltui.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllltui.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllltui.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllltui.ll Tue Dec 4 12:14:57 2018
@@ -1,7 +1,7 @@
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: llc --relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllnesll.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllnesll.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllnesll.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllnesll.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i64 0, align 8
@@ -15,6 +15,19 @@ define i64 @test_llnesll(i64 %a, i64 %b)
; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llnesll:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: addic r4, r3, -1
+; CHECK-BE-NEXT: subfe r3, r4, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llnesll:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addic r4, r3, -1
+; CHECK-LE-NEXT: subfe r3, r4, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = zext i1 %cmp to i64
@@ -28,6 +41,19 @@ define i64 @test_llnesll_sext(i64 %a, i6
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llnesll_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: subfic r3, r3, 0
+; CHECK-BE-NEXT: subfe r3, r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llnesll_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: subfic r3, r3, 0
+; CHECK-LE-NEXT: subfe r3, r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = sext i1 %cmp to i64
@@ -40,6 +66,17 @@ define i64 @test_llnesll_z(i64 %a) {
; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llnesll_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addic r4, r3, -1
+; CHECK-BE-NEXT: subfe r3, r4, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llnesll_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: addic r4, r3, -1
+; CHECK-LE-NEXT: subfe r3, r4, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = zext i1 %cmp to i64
@@ -52,6 +89,17 @@ define i64 @test_llnesll_sext_z(i64 %a)
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llnesll_sext_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: subfic r3, r3, 0
+; CHECK-BE-NEXT: subfe r3, r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llnesll_sext_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: subfic r3, r3, 0
+; CHECK-LE-NEXT: subfe r3, r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = sext i1 %cmp to i64
@@ -61,13 +109,30 @@ entry:
define void @test_llnesll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llnesll_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
-; CHECK-NEXT: addic r5, r3, -1
-; CHECK-NEXT: subfe r3, r5, r3
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-NEXT: addic r4, r3, -1
+; CHECK-NEXT: subfe r3, r4, r3
+; CHECK-NEXT: std r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llnesll_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: addic r5, r3, -1
+; CHECK-BE-NEXT: subfe r3, r5, r3
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llnesll_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: addic r4, r3, -1
+; CHECK-LE-NEXT: subfe r3, r4, r3
+; CHECK-LE-NEXT: std r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = zext i1 %cmp to i64
@@ -78,13 +143,30 @@ entry:
define void @test_llnesll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llnesll_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llnesll_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: subfic r3, r3, 0
+; CHECK-BE-NEXT: subfe r3, r3, r3
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llnesll_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: subfic r3, r3, 0
+; CHECK-LE-NEXT: subfe r3, r3, r3
+; CHECK-LE-NEXT: std r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = sext i1 %cmp to i64
@@ -95,12 +177,27 @@ entry:
define void @test_llnesll_z_store(i64 %a) {
; CHECK-LABEL: test_llnesll_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: addic r5, r3, -1
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: subfe r3, r5, r3
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llnesll_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: addic r5, r3, -1
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: subfe r3, r5, r3
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llnesll_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: addic r5, r3, -1
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: subfe r3, r5, r3
+; CHECK-LE-NEXT: std r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = zext i1 %cmp to i64
@@ -111,12 +208,27 @@ entry:
define void @test_llnesll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_llnesll_sext_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: subfic r3, r3, 0
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: subfe r3, r3, r3
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llnesll_sext_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: subfic r3, r3, 0
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: subfe r3, r3, r3
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llnesll_sext_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: subfic r3, r3, 0
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: subfe r3, r3, r3
+; CHECK-LE-NEXT: std r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = sext i1 %cmp to i64
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllneull.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllneull.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllneull.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllneull.ll Tue Dec 4 12:14:57 2018
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i64 0, align 8
@@ -15,6 +15,19 @@ define i64 @test_llneull(i64 %a, i64 %b)
; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llneull:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: addic r4, r3, -1
+; CHECK-BE-NEXT: subfe r3, r4, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llneull:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addic r4, r3, -1
+; CHECK-LE-NEXT: subfe r3, r4, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = zext i1 %cmp to i64
@@ -28,6 +41,19 @@ define i64 @test_llneull_sext(i64 %a, i6
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llneull_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: subfic r3, r3, 0
+; CHECK-BE-NEXT: subfe r3, r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llneull_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: subfic r3, r3, 0
+; CHECK-LE-NEXT: subfe r3, r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = sext i1 %cmp to i64
@@ -40,6 +66,17 @@ define i64 @test_llneull_z(i64 %a) {
; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llneull_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addic r4, r3, -1
+; CHECK-BE-NEXT: subfe r3, r4, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llneull_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: addic r4, r3, -1
+; CHECK-LE-NEXT: subfe r3, r4, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = zext i1 %cmp to i64
@@ -52,6 +89,17 @@ define i64 @test_llneull_sext_z(i64 %a)
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llneull_sext_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: subfic r3, r3, 0
+; CHECK-BE-NEXT: subfe r3, r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llneull_sext_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: subfic r3, r3, 0
+; CHECK-LE-NEXT: subfe r3, r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = sext i1 %cmp to i64
@@ -61,13 +109,30 @@ entry:
define void @test_llneull_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llneull_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
-; CHECK-NEXT: addic r5, r3, -1
-; CHECK-NEXT: subfe r3, r5, r3
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-NEXT: addic r4, r3, -1
+; CHECK-NEXT: subfe r3, r4, r3
+; CHECK-NEXT: std r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llneull_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: addic r5, r3, -1
+; CHECK-BE-NEXT: subfe r3, r5, r3
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llneull_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: addic r4, r3, -1
+; CHECK-LE-NEXT: subfe r3, r4, r3
+; CHECK-LE-NEXT: std r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = zext i1 %cmp to i64
@@ -78,13 +143,30 @@ entry:
define void @test_llneull_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llneull_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob at toc@ha
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llneull_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-BE-NEXT: subfic r3, r3, 0
+; CHECK-BE-NEXT: subfe r3, r3, r3
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llneull_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob at toc@ha
+; CHECK-LE-NEXT: subfic r3, r3, 0
+; CHECK-LE-NEXT: subfe r3, r3, r3
+; CHECK-LE-NEXT: std r3, glob at toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = sext i1 %cmp to i64
@@ -95,12 +177,27 @@ entry:
define void @test_llneull_z_store(i64 %a) {
; CHECK-LABEL: test_llneull_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: addic r5, r3, -1
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: subfe r3, r5, r3
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llneull_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: addic r5, r3, -1
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: subfe r3, r5, r3
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llneull_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: addic r5, r3, -1
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: subfe r3, r5, r3
+; CHECK-LE-NEXT: std r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = zext i1 %cmp to i64
@@ -111,12 +208,27 @@ entry:
define void @test_llneull_sext_z_store(i64 %a) {
; CHECK-LABEL: test_llneull_sext_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
; CHECK-NEXT: subfic r3, r3, 0
-; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: subfe r3, r3, r3
-; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: std r3, glob at toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_llneull_sext_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-BE-NEXT: subfic r3, r3, 0
+; CHECK-BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-BE-NEXT: subfe r3, r3, r3
+; CHECK-BE-NEXT: std r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_llneull_sext_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: subfic r3, r3, 0
+; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
+; CHECK-LE-NEXT: subfe r3, r3, r3
+; CHECK-LE-NEXT: std r3, glob at toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = sext i1 %cmp to i64
Modified: llvm/trunk/test/CodeGen/PowerPC/toc-float.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/toc-float.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/toc-float.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/toc-float.ll Tue Dec 4 12:14:57 2018
@@ -1,5 +1,5 @@
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 <%s | FileCheck -check-prefix=CHECK-P9 %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 <%s | FileCheck -check-prefix=CHECK-P8 %s
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 <%s | FileCheck -check-prefix=CHECK-P9 %s
+; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 <%s | FileCheck -check-prefix=CHECK-P8 %s
; As the constant could be represented as float, a float is
; loaded from constant pool.
Modified: llvm/trunk/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll Tue Dec 4 12:14:57 2018
@@ -1,6 +1,6 @@
-; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: llc -relocation-model=pic -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -mattr=-direct-move | FileCheck %s
-; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: llc -relocation-model=pic -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -mattr=-direct-move | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -mattr=-direct-move | FileCheck %s -check-prefix=CHECK-P9
Modified: llvm/trunk/test/CodeGen/PowerPC/xray-tail-call-sled.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/xray-tail-call-sled.ll?rev=348298&r1=348297&r2=348298&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/xray-tail-call-sled.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/xray-tail-call-sled.ll Tue Dec 4 12:14:57 2018
@@ -1,4 +1,4 @@
-; RUN: llc -filetype=asm -o - -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+; RUN: llc -filetype=asm -relocation-model=pic -o - -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
define i32 @callee() nounwind noinline uwtable "function-instrument"="xray-always" {
; CHECK-LABEL: .Ltmp0:
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