[PATCH] D55223: [SelectionDAG] Don't pass on DemandedElts when handling SCALAR_TO_VECTOR

[Rhys Perry via Phabricator via llvm-commits]

pendingchaos created this revision.
pendingchaos added reviewers: rampitec, RKSimon, craig.topper.
Herald added subscribers: nhaehnle, jvesely.

Fixes an assertion:

llc: lib/CodeGen/SelectionDAG/SelectionDAG.cpp:2200: llvm::KnownBits llvm::SelectionDAG::computeKnownBits(llvm::SDValue, const llvm::APInt&, unsigned int) const: Assertion `(!Op.getValueType().isVector() || NumElts == Op.getValueType().getVectorNumElements()) && "Unexpected vector size"' failed.


Repository:
  rL LLVM

https://reviews.llvm.org/D55223

Files:
  lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  test/CodeGen/AMDGPU/computeKnownBits-scalar-to-vector-crash.ll


Index: test/CodeGen/AMDGPU/computeKnownBits-scalar-to-vector-crash.ll
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/computeKnownBits-scalar-to-vector-crash.ll
@@ -0,0 +1,10 @@
+; RUN: llc -march=amdgcn -mcpu=gfx802 -verify-machineinstrs < %s
+
+define <2 x i16> @main(<2 x float>) #0 {
+  %2 = bitcast <2 x float> %0 to <4 x i16>
+  %3 = shufflevector <4 x i16> %2, <4 x i16> undef, <2 x i32> <i32 0, i32 undef>
+  %4 = extractelement <4 x i16> %2, i32 0
+  %5 = insertelement <2 x i16> %3, i16 %4, i32 0
+  ret <2 x i16> %5
+}
+
Index: lib/CodeGen/SelectionDAG/SelectionDAG.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -2352,7 +2352,7 @@
       break;
 
     SDValue N0 = Op.getOperand(0);
-    Known = computeKnownBits(N0, DemandedElts, Depth + 1);
+    Known = computeKnownBits(N0, Depth + 1);
     if (N0.getValueSizeInBits() != BitWidth)
       Known = Known.trunc(BitWidth);
 


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