[llvm] r348137 - [AArch64] Add command-line option for SSBS
Pablo Barrio via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 3 06:00:47 PST 2018
Author: pabbar01
Date: Mon Dec 3 06:00:47 2018
New Revision: 348137
URL: http://llvm.org/viewvc/llvm-project?rev=348137&view=rev
Log:
[AArch64] Add command-line option for SSBS
Summary:
SSBS (Speculative Store Bypass Safe) is only mandatory from 8.5
onwards but is optional from Armv8.0-A. This patch adds a command
line option to enable SSBS, as it was previously only possible to
enable by selecting -march=armv8.5-a.
Similar patch upstream in GNU binutils:
https://sourceware.org/ml/binutils/2018-09/msg00274.html
Reviewers: olista01, samparker, aemerson
Reviewed By: samparker
Subscribers: javed.absar, kristof.beyls, kristina, llvm-commits
Differential Revision: https://reviews.llvm.org/D54629
Added:
llvm/trunk/test/MC/AArch64/armv8.5a-ssbs-error.s
- copied, changed from r348132, llvm/trunk/test/MC/AArch64/armv8.5a-specrestrict-error.s
llvm/trunk/test/MC/AArch64/armv8.5a-ssbs.s
llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-ssbs.txt
Removed:
llvm/trunk/test/MC/AArch64/armv8.5a-specrestrict-error.s
Modified:
llvm/trunk/include/llvm/Support/AArch64TargetParser.def
llvm/trunk/include/llvm/Support/AArch64TargetParser.h
llvm/trunk/lib/Target/AArch64/AArch64.td
llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td
llvm/trunk/test/MC/AArch64/armv8.5a-specrestrict.s
llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-specrestrict.txt
llvm/trunk/unittests/Support/TargetParserTest.cpp
Modified: llvm/trunk/include/llvm/Support/AArch64TargetParser.def
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/AArch64TargetParser.def?rev=348137&r1=348136&r2=348137&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/AArch64TargetParser.def (original)
+++ llvm/trunk/include/llvm/Support/AArch64TargetParser.def Mon Dec 3 06:00:47 2018
@@ -72,6 +72,7 @@ AARCH64_ARCH_EXT_NAME("sve", AArch6
AARCH64_ARCH_EXT_NAME("rcpc", AArch64::AEK_RCPC, "+rcpc", "-rcpc")
AARCH64_ARCH_EXT_NAME("rng", AArch64::AEK_RAND, "+rand", "-rand")
AARCH64_ARCH_EXT_NAME("memtag", AArch64::AEK_MTE, "+mte", "-mte")
+AARCH64_ARCH_EXT_NAME("ssbs", AArch64::AEK_SSBS, "+ssbs", "-ssbs")
#undef AARCH64_ARCH_EXT_NAME
#ifndef AARCH64_CPU_NAME
Modified: llvm/trunk/include/llvm/Support/AArch64TargetParser.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/AArch64TargetParser.h?rev=348137&r1=348136&r2=348137&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/AArch64TargetParser.h (original)
+++ llvm/trunk/include/llvm/Support/AArch64TargetParser.h Mon Dec 3 06:00:47 2018
@@ -47,6 +47,7 @@ enum ArchExtKind : unsigned {
AEK_FP16FML = 1 << 17,
AEK_RAND = 1 << 18,
AEK_MTE = 1 << 19,
+ AEK_SSBS = 1 << 20,
};
enum class ArchKind {
Modified: llvm/trunk/lib/Target/AArch64/AArch64.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64.td?rev=348137&r1=348136&r2=348137&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64.td Mon Dec 3 06:00:47 2018
@@ -306,6 +306,9 @@ def FeatureFRInt3264 : SubtargetFeature<
def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict",
"true", "Enable architectural speculation restriction" >;
+def FeatureSSBS : SubtargetFeature<"ssbs", "HasSSBS",
+ "true", "Enable Speculative Store Bypass Safe bit" >;
+
def FeatureSpecCtrl : SubtargetFeature<"specctrl", "HasSpecCtrl", "true",
"Enable speculation control barrier" >;
@@ -349,7 +352,7 @@ def HasV8_4aOps : SubtargetFeature<"v8.4
def HasV8_5aOps : SubtargetFeature<
"v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
[HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict,
- FeatureSpecCtrl, FeaturePredCtrl, FeatureCacheDeepPersist,
+ FeatureSSBS, FeatureSpecCtrl, FeaturePredCtrl, FeatureCacheDeepPersist,
FeatureBranchTargetId]
>;
Modified: llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h?rev=348137&r1=348136&r2=348137&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h Mon Dec 3 06:00:47 2018
@@ -127,6 +127,7 @@ protected:
bool HasFRInt3264 = false;
bool HasSpecRestrict = false;
bool HasSpecCtrl = false;
+ bool HasSSBS = false;
bool HasPredCtrl = false;
bool HasCCDP = false;
bool HasBTI = false;
@@ -355,6 +356,7 @@ public:
bool hasFRInt3264() const { return HasFRInt3264; }
bool hasSpecRestrict() const { return HasSpecRestrict; }
bool hasSpecCtrl() const { return HasSpecCtrl; }
+ bool hasSSBS() const { return HasSSBS; }
bool hasPredCtrl() const { return HasPredCtrl; }
bool hasCCDP() const { return HasCCDP; }
bool hasBTI() const { return HasBTI; }
Modified: llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td?rev=348137&r1=348136&r2=348137&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td Mon Dec 3 06:00:47 2018
@@ -343,7 +343,7 @@ def : PState<"UAO", 0b00011>;
let Requires = [{ {AArch64::FeatureDIT} }] in
def : PState<"DIT", 0b11010>;
// v8.5a Spectre Mitigation
-let Requires = [{ {AArch64::FeatureSpecRestrict} }] in
+let Requires = [{ {AArch64::FeatureSSBS} }] in
def : PState<"SSBS", 0b11001>;
// v8.5a Memory Tagging Extension
let Requires = [{ {AArch64::FeatureMTE} }] in
@@ -1444,7 +1444,7 @@ def : RWSysReg<"ZCR_EL12", 0b11,
// V8.5a Spectre mitigation SSBS register
// Op0 Op1 CRn CRm Op2
-let Requires = [{ {AArch64::FeatureSpecRestrict} }] in
+let Requires = [{ {AArch64::FeatureSSBS} }] in
def : RWSysReg<"SSBS", 0b11, 0b011, 0b0100, 0b0010, 0b110>;
// v8.5a Memory Tagging Extension
Removed: llvm/trunk/test/MC/AArch64/armv8.5a-specrestrict-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.5a-specrestrict-error.s?rev=348136&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/armv8.5a-specrestrict-error.s (original)
+++ llvm/trunk/test/MC/AArch64/armv8.5a-specrestrict-error.s (removed)
@@ -1,10 +0,0 @@
-// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+specrestrict < %s 2>&1 | FileCheck %s
-// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+v8.5a < %s 2>&1 | FileCheck %s
-// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-specrestrict < %s 2>&1 | FileCheck %s --check-prefix=NOSPECID
-
-msr SSBS, #2
-
-// CHECK: error: immediate must be an integer in range [0, 1].
-// CHECK-NEXT: msr SSBS, #2
-// NOSPECID: error: expected writable system register or pstate
-// NOSPECID-NEXT: msr {{ssbs|SSBS}}, #2
Modified: llvm/trunk/test/MC/AArch64/armv8.5a-specrestrict.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.5a-specrestrict.s?rev=348137&r1=348136&r2=348137&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/armv8.5a-specrestrict.s (original)
+++ llvm/trunk/test/MC/AArch64/armv8.5a-specrestrict.s Mon Dec 3 06:00:47 2018
@@ -51,19 +51,3 @@ msr SCXTNUM_EL12, x4
// NOSPECID-NEXT: {{scxtnum_el3|SCXTNUM_EL3}}
// NOSPECID: error: expected writable system register
// NOSPECID-NEXT: {{scxtnum_el12|SCXTNUM_EL12}}
-
-mrs x2, SSBS
-
-// CHECK: mrs x2, {{ssbs|SSBS}} // encoding: [0xc2,0x42,0x3b,0xd5]
-// NOSPECID: error: expected readable system register
-// NOSPECID-NEXT: mrs x2, {{ssbs|SSBS}}
-
-msr SSBS, x3
-msr SSBS, #1
-
-// CHECK: msr {{ssbs|SSBS}}, x3 // encoding: [0xc3,0x42,0x1b,0xd5]
-// CHECK: msr {{ssbs|SSBS}}, #1 // encoding: [0x3f,0x41,0x03,0xd5]
-// NOSPECID: error: expected writable system register or pstate
-// NOSPECID-NEXT: msr {{ssbs|SSBS}}, x3
-// NOSPECID: error: expected writable system register or pstate
-// NOSPECID-NEXT: msr {{ssbs|SSBS}}, #1
Copied: llvm/trunk/test/MC/AArch64/armv8.5a-ssbs-error.s (from r348132, llvm/trunk/test/MC/AArch64/armv8.5a-specrestrict-error.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.5a-ssbs-error.s?p2=llvm/trunk/test/MC/AArch64/armv8.5a-ssbs-error.s&p1=llvm/trunk/test/MC/AArch64/armv8.5a-specrestrict-error.s&r1=348132&r2=348137&rev=348137&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/armv8.5a-specrestrict-error.s (original)
+++ llvm/trunk/test/MC/AArch64/armv8.5a-ssbs-error.s Mon Dec 3 06:00:47 2018
@@ -1,6 +1,6 @@
-// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+specrestrict < %s 2>&1 | FileCheck %s
-// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+v8.5a < %s 2>&1 | FileCheck %s
-// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-specrestrict < %s 2>&1 | FileCheck %s --check-prefix=NOSPECID
+// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+ssbs < %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+v8.5a < %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-ssbs < %s 2>&1 | FileCheck %s --check-prefix=NOSPECID
msr SSBS, #2
Added: llvm/trunk/test/MC/AArch64/armv8.5a-ssbs.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.5a-ssbs.s?rev=348137&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/armv8.5a-ssbs.s (added)
+++ llvm/trunk/test/MC/AArch64/armv8.5a-ssbs.s Mon Dec 3 06:00:47 2018
@@ -0,0 +1,19 @@
+// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+ssbs < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+v8.5a < %s | FileCheck %s
+// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-ssbs < %s 2>&1 | FileCheck %s --check-prefix=NOSPECID
+
+mrs x2, SSBS
+
+// CHECK: mrs x2, {{ssbs|SSBS}} // encoding: [0xc2,0x42,0x3b,0xd5]
+// NOSPECID: error: expected readable system register
+// NOSPECID-NEXT: mrs x2, {{ssbs|SSBS}}
+
+msr SSBS, x3
+msr SSBS, #1
+
+// CHECK: msr {{ssbs|SSBS}}, x3 // encoding: [0xc3,0x42,0x1b,0xd5]
+// CHECK: msr {{ssbs|SSBS}}, #1 // encoding: [0x3f,0x41,0x03,0xd5]
+// NOSPECID: error: expected writable system register or pstate
+// NOSPECID-NEXT: msr {{ssbs|SSBS}}, x3
+// NOSPECID: error: expected writable system register or pstate
+// NOSPECID-NEXT: msr {{ssbs|SSBS}}, #1
Modified: llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-specrestrict.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-specrestrict.txt?rev=348137&r1=348136&r2=348137&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-specrestrict.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-specrestrict.txt Mon Dec 3 06:00:47 2018
@@ -40,13 +40,3 @@
# NOSPECID: msr S3_4_C13_C0_7, x6
# NOSPECID: msr S3_6_C13_C0_7, x5
# NOSPECID: msr S3_5_C13_C0_7, x4
-
-[0x3f 0x41 0x03 0xd5]
-[0xc3 0x42 0x1b 0xd5]
-[0xc2 0x42 0x3b 0xd5]
-# CHECK: msr SSBS, #1
-# CHECK: msr SSBS, x3
-# CHECK: mrs x2, SSBS
-# NOSPECID: msr S0_3_C4_C1_1, xzr
-# NOSPECID: msr S3_3_C4_C2_6, x3
-# NOSPECID: mrs x2, S3_3_C4_C2_6
Added: llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-ssbs.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-ssbs.txt?rev=348137&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-ssbs.txt (added)
+++ llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-ssbs.txt Mon Dec 3 06:00:47 2018
@@ -0,0 +1,13 @@
+# RUN: llvm-mc -triple=aarch64 -mattr=+ssbs -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -mattr=-ssbs -disassemble < %s | FileCheck %s --check-prefix=NOSPECID
+
+[0x3f 0x41 0x03 0xd5]
+[0xc3 0x42 0x1b 0xd5]
+[0xc2 0x42 0x3b 0xd5]
+# CHECK: msr SSBS, #1
+# CHECK: msr SSBS, x3
+# CHECK: mrs x2, SSBS
+# NOSPECID: msr S0_3_C4_C1_1, xzr
+# NOSPECID: msr S3_3_C4_C2_6, x3
+# NOSPECID: mrs x2, S3_3_C4_C2_6
Modified: llvm/trunk/unittests/Support/TargetParserTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/Support/TargetParserTest.cpp?rev=348137&r1=348136&r2=348137&view=diff
==============================================================================
--- llvm/trunk/unittests/Support/TargetParserTest.cpp (original)
+++ llvm/trunk/unittests/Support/TargetParserTest.cpp Mon Dec 3 06:00:47 2018
@@ -508,7 +508,7 @@ TEST(TargetParserTest, testARMExtension)
}
TEST(TargetParserTest, ARMFPUVersion) {
- for (ARM::FPUKind FK = static_cast<ARM::FPUKind>(0);
+ for (ARM::FPUKind FK = static_cast<ARM::FPUKind>(0);
FK <= ARM::FPUKind::FK_LAST;
FK = static_cast<ARM::FPUKind>(static_cast<unsigned>(FK) + 1))
if (FK == ARM::FK_LAST || ARM::getFPUName(FK) == "invalid" ||
@@ -992,7 +992,8 @@ TEST(TargetParserTest, AArch64ArchExtFea
{"dotprod", "nodotprod", "+dotprod", "-dotprod"},
{"rcpc", "norcpc", "+rcpc", "-rcpc" },
{"rng", "norng", "+rand", "-rand"},
- {"memtag", "nomemtag", "+mte", "-mte"}};
+ {"memtag", "nomemtag", "+mte", "-mte"},
+ {"ssbs", "nossbs", "+ssbs", "-ssbs"}};
for (unsigned i = 0; i < array_lengthof(ArchExt); i++) {
EXPECT_EQ(StringRef(ArchExt[i][2]),
More information about the llvm-commits
mailing list