[PATCH] D55192: [PowerPC] VSX register support for inline assembly

[Zhang Kang via Phabricator via llvm-commits]

ZhangKang created this revision.
ZhangKang added reviewers: nemanjai, echristo, hfinkel, jsji, steven.zhang.
Herald added a subscriber: eraman.

The patch is to add the VSX register support for inline assembly.

Before this patch, below case will get an error.

  $ cat test.c
  #include <altivec.h>
  unsigned int a=0;
  int main () {
    unsigned int *dbell=&a;
    int d;
   __asm__ __volatile__
                  ("lxvw4x %%vs32, 0, %2\n\t"
                   "stxvw4x %%vs32, 0, %1"
                   : "=m"(*(volatile unsigned int*)(dbell)) 
                   : "r" (dbell),
                      "r" (&d)
                   : "vs32");  
  
    return 0;
  }

Below is the error information.

  $ clang -c test.c
  t1.c:12:20: error: unknown register name 'vs32' in asm
                   : "vs32");  
                     ^
  1 error generated.

After this patch, we can get inline assembly we expected without error.


https://reviews.llvm.org/D55192

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/test/CodeGen/inline-asm-matching-ppc-vsx.c


Index: clang/test/CodeGen/inline-asm-matching-ppc-vsx.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/inline-asm-matching-ppc-vsx.c
@@ -0,0 +1,22 @@
+// REQUIRES: powerpc-registered-target
+
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -target-feature +vsx \
+// RUN:   -emit-llvm %s -o - | FileCheck %s
+
+// This case is to test VSX register support in the clobbers list for inline asm.
+void testVSX (void) {
+  unsigned int a = 0;
+  unsigned int *dbell=&a;
+  int d;
+  __asm__ __volatile__ (
+    "lxvw4x  %%vs32, 0, %2\n\t"
+    "stxvw4x %%vs32, 0, %1"
+    : "=m"(*(volatile unsigned int*)(dbell))
+    : "r" (dbell), "r" (&d)
+    : "vs32"
+  );
+}
+
+// The vs32 register in the clobbers list should be archieved as v0 in the 
+// IR clobbers list. 
+// CHECK: call void asm sideeffect "lxvw4x %vs32, 0, $2\0A\09stxvw4x %vs32, 0, $1", "=*m,r,r,~{v0}"
Index: clang/lib/Basic/Targets/PPC.cpp
===================================================================
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -405,6 +405,22 @@
     {{"fr20"}, "f20"}, {{"fr21"}, "f21"}, {{"fr22"}, "f22"}, {{"fr23"}, "f23"},
     {{"fr24"}, "f24"}, {{"fr25"}, "f25"}, {{"fr26"}, "f26"}, {{"fr27"}, "f27"},
     {{"fr28"}, "f28"}, {{"fr29"}, "f29"}, {{"fr30"}, "f30"}, {{"fr31"}, "f31"},
+    {{"vs0"}, "f0"},   {{"vs1"}, "f1"},   {{"vs2"}, "f2"},   {{"vs3"}, "f3"},
+    {{"vs4"}, "f4"},   {{"vs5"}, "f5"},   {{"vs6"}, "f6"},   {{"vs7"}, "f7"},
+    {{"vs8"}, "f8"},   {{"vs9"}, "f9"},   {{"vs10"}, "f10"}, {{"vs11"}, "f11"},
+    {{"vs12"}, "f12"}, {{"vs13"}, "f13"}, {{"vs14"}, "f14"}, {{"vs15"}, "f15"},
+    {{"vs16"}, "f16"}, {{"vs17"}, "f17"}, {{"vs18"}, "f18"}, {{"vs19"}, "f19"},
+    {{"vs20"}, "f20"}, {{"vs21"}, "f21"}, {{"vs22"}, "f22"}, {{"vs23"}, "f23"},
+    {{"vs24"}, "f24"}, {{"vs25"}, "f25"}, {{"vs26"}, "f26"}, {{"vs27"}, "f27"},
+    {{"vs28"}, "f28"}, {{"vs29"}, "f29"}, {{"vs30"}, "f30"}, {{"vs31"}, "f31"},
+    {{"vs32"}, "v0"},  {{"vs33"}, "v1"},  {{"vs34"}, "v2"},  {{"vs35"}, "v3"},
+    {{"vs36"}, "v4"},  {{"vs37"}, "v5"},  {{"vs38"}, "v6"},  {{"vs39"}, "v7"},
+    {{"vs40"}, "v8"},  {{"vs41"}, "v9"},  {{"vs42"}, "v10"}, {{"vs43"}, "v11"},
+    {{"vs44"}, "v12"}, {{"vs45"}, "v13"}, {{"vs46"}, "v14"}, {{"vs47"}, "v15"},
+    {{"vs48"}, "v16"}, {{"vs49"}, "v17"}, {{"vs50"}, "v18"}, {{"vs51"}, "v19"},
+    {{"vs52"}, "v20"}, {{"vs53"}, "v21"}, {{"vs54"}, "v22"}, {{"vs55"}, "v23"},
+    {{"vs56"}, "v24"}, {{"vs57"}, "v25"}, {{"vs58"}, "v26"}, {{"vs59"}, "v27"},
+    {{"vs60"}, "v28"}, {{"vs61"}, "v29"}, {{"vs62"}, "v30"}, {{"vs63"}, "v31"},
     {{"cc"}, "cr0"},
 };
 


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