[PATCH] D55165: [X86] Teach LowerMUL for vXi8 to unpack constant RHS.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: RKSimon, spatel.

We need to unpackl and unpackh the operands to use two vXi16 multiplies. Previously it looks like the low unpack would get constant folded at least in the 128-bit case after shuffle lowering turned the unpackl into ZERO_EXTEND_VECTOR_INREG and X86 custom DAG combined it. The same doesn't happen for the high half. So we'd load a constant and then shuffle it. But the low half would just be loaded and used by the multiply directly.

After this patch we now end up with a constant pool entry for the low and high unpacks separately with no shuffle operations.

This is a step towards removing custom constant folding for ZERO_EXTEND_VECTOR_INREG/SIGN_EXTEND_VECTOR_INREG in the X86 backend. I'm going to look at LowerMULH next.


Repository:
  rL LLVM

https://reviews.llvm.org/D55165

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/combine-mul.ll
  test/CodeGen/X86/pmul.ll
  test/CodeGen/X86/vector-mul.ll
  test/CodeGen/X86/vector-shift-shl-128.ll
  test/CodeGen/X86/vector-shift-shl-256.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D55165.176263.patch
Type: text/x-patch
Size: 28884 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20181201/dbd12352/attachment.bin>