[PATCH] D54882: [AMDGPU] Add sdwa support for ADD|SUB U64 decomposed Pseudos

[Ron Lieberman via Phabricator via llvm-commits]

ronlieb marked 6 inline comments as done.
ronlieb added inline comments.


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Comment at: lib/Target/AMDGPU/SIPeepholeSDWA.cpp:862
+  // if no reference to VCC in current Func, its usable.
+  if (MRI->reg_empty(AMDGPU::VCC))
+    return true;
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rampitec wrote:
> Not necessarily, a vcc_lo or hcc_hi can be used.
seems like computeRegisterLiveness is a much better approach to determining VCC liveness than the clunky function  VCCUsable, so i can simply toss this function out and use the computeRegisterLiveness which also handles the Subregs of VCC


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Comment at: test/CodeGen/AMDGPU/sdwa-ops.mir:1
+# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=si-peephole-sdwa -o - %s | FileCheck -check-prefix=GFX9 %s
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=si-peephole-sdwa -o - %s | FileCheck -check-prefix=GFX9 %s
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rampitec wrote:
> I do not see a test with modifiers.
i am having difficulty trying to construct a V_ADD_I32 or V_ADDC_U32 instruction with an abs or neg modifiers. In particular, the architecture ref gfx9 has comments like the following regarding input modifiers for vop1, vop2, vop3 

"In general, negation and absolute value are only supported for floating point input operands (operands with a type of F16, F32, or F64); they are not supported for integer or untyped inputs."

Do you know of an MIR example which has modifiers?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D54882/new/

https://reviews.llvm.org/D54882