[PATCH] D52977: [RISCV] Introduce codegen patterns for instructions introduced in RV64I

[James Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


================
Comment at: llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td:916
+def : Pat<(sra (sext_inreg GPR:$rs1, i32), GPR:$rs2),
+          (SRAW GPR:$rs1, GPR:$rs2)>;
+def : Pat<(sra (sext_inreg GPR:$rs1, i32), (and GPR:$rs2, immshifti32)),
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efriedma wrote:
> These shift-right patterns are sort of suspicious.  In particular, what happens if the shift amount is >= 32?  For example, consider the following function:
> 
>   long long x(long long y, int s) {
>     return ((long long)(int)y)>>s;
>   }
> 
> `x(1, 32)` should return 0.
Agreed, this currently produces a single `sraw a0, a0, a1` for the body of the function, but SRAW only looks at `rs2[4:0]` ie the shift is modulo 32. The older versions of this patch set actually got this right, producing the correct `sext.w a0, a0 ; sra a0, a0, a1` (which is what GCC also does).


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D52977/new/

https://reviews.llvm.org/D52977