[PATCH] D55126: [DAGCombiner] narrow truncated vector binops when legal

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: andreadb, craig.topper, lebedev.ri, RKSimon.
Herald added a subscriber: mcrosier.

This is the smallest vector enhancement I could find to D54640 <https://reviews.llvm.org/D54640>. Here, we're allowing narrowing to only legal vector ops because we'll see regressions without that. All of the test diffs are wins from what I can tell. With AVX/AVX512, we can shrink ymm/zmm ops to xmm.

x86 vector multiplies are the problem case due to the patchwork ISA, and it's not clear to me if we can dance around those regressions using TLI hooks or if we need preliminary patches to plug those holes.

This patch probably makes some of the custom x86 code in "combineTruncatedArithmetic" unnecessary, but I'd rather wait to try removing anything from there until we're sure this code doesn't cause regressions for other targets and evolves to handle more cases.


https://reviews.llvm.org/D55126

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/X86/vector-trunc-math-widen.ll
  test/CodeGen/X86/vector-trunc-math.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D55126.176125.patch
Type: text/x-patch
Size: 46223 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20181130/161a8204/attachment.bin>