[PATCH] D55008: [RISCV] Add CSR instruction aliases (imm. operands)

[Alex Bradbury via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL347991: [RISCV] Add additional CSR instruction aliases (imm. operands) (authored by asb, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D55008?vs=175704&id=176106#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D55008/new/

https://reviews.llvm.org/D55008

Files:
  llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/trunk/test/MC/RISCV/rvi-aliases-valid.s


Index: llvm/trunk/test/MC/RISCV/rvi-aliases-valid.s
===================================================================
--- llvm/trunk/test/MC/RISCV/rvi-aliases-valid.s
+++ llvm/trunk/test/MC/RISCV/rvi-aliases-valid.s
@@ -181,6 +181,26 @@
 # CHECK-S-OBJ: csrci sscratch, 17
 csrci 0x140, 0x11
 
+# CHECK-S-OBJ-NOALIAS: csrrwi zero, 336, 7
+# CHECK-S-OBJ: csrwi 336, 7
+csrw 0x150, 7
+# CHECK-S-OBJ-NOALIAS: csrrsi zero, 336, 7
+# CHECK-S-OBJ: csrsi 336, 7
+csrs 0x150, 7
+# CHECK-S-OBJ-NOALIAS: csrrci zero, 336, 7
+# CHECK-S-OBJ: csrci 336, 7
+csrc 0x150, 7
+
+# CHECK-S-OBJ-NOALIAS: csrrwi t0, 336, 15
+# CHECK-S-OBJ: csrrwi t0, 336, 15
+csrrw t0, 0x150, 0xf
+# CHECK-S-OBJ-NOALIAS: csrrsi t0, 4095, 16
+# CHECK-S-OBJ: csrrsi t0, 4095, 16
+csrrs t0, 0xfff, 0x10
+# CHECK-S-OBJ-NOALIAS: csrrci t0, sscratch, 17
+# CHECK-S-OBJ: csrrci t0, sscratch, 17
+csrrc t0, 0x140, 0x11
+
 # CHECK-S-OBJ-NOALIAS: sfence.vma zero, zero
 # CHECK-S-OBJ: sfence.vma
 sfence.vma
Index: llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td
===================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td
@@ -580,6 +580,16 @@
 def : InstAlias<"csrsi $csr, $imm", (CSRRSI X0, csr_sysreg:$csr, uimm5:$imm)>;
 def : InstAlias<"csrci $csr, $imm", (CSRRCI X0, csr_sysreg:$csr, uimm5:$imm)>;
 
+let EmitPriority = 0 in {
+def : InstAlias<"csrw $csr, $imm", (CSRRWI X0, csr_sysreg:$csr, uimm5:$imm)>;
+def : InstAlias<"csrs $csr, $imm", (CSRRSI X0, csr_sysreg:$csr, uimm5:$imm)>;
+def : InstAlias<"csrc $csr, $imm", (CSRRCI X0, csr_sysreg:$csr, uimm5:$imm)>;
+
+def : InstAlias<"csrrw $rd, $csr, $imm", (CSRRWI GPR:$rd, csr_sysreg:$csr, uimm5:$imm)>;
+def : InstAlias<"csrrs $rd, $csr, $imm", (CSRRSI GPR:$rd, csr_sysreg:$csr, uimm5:$imm)>;
+def : InstAlias<"csrrc $rd, $csr, $imm", (CSRRCI GPR:$rd, csr_sysreg:$csr, uimm5:$imm)>;
+}
+
 def : InstAlias<"sfence.vma",     (SFENCE_VMA      X0, X0)>;
 def : InstAlias<"sfence.vma $rs", (SFENCE_VMA GPR:$rs, X0)>;
 


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