[llvm] r347988 - [RISCV] Add UNIMP instruction (32- and 16-bit forms)

[Alex Bradbury via llvm-commits]

Author: asb
Date: Fri Nov 30 05:39:17 2018
New Revision: 347988

URL: http://llvm.org/viewvc/llvm-project?rev=347988&view=rev
Log:
[RISCV] Add UNIMP instruction (32- and 16-bit forms)

This patch adds support for UNIMP in both 32- and 16-bit forms. The 32-bit 
form can be seen as a variant of the ECALL/EBREAK/etc. family of instructions. 
The 16-bit form is just all zeroes, which isn't a valid RISC-V instruction, 
but still follows the 16-bit instruction form (i.e. bits 0-1 != 11).

Until recently unimp was undocumented and supported just by binutils, which 
printed unimp for either the 16 or 32-bit form. Both forms are now documented 
<https://github.com/riscv/riscv-asm-manual/pull/20> and binutils now supports 
c.unimp <https://sourceware.org/ml/binutils-cvs/2018-11/msg00179.html>.

Differential Revision: https://reviews.llvm.org/D54316
Patch by Luís Marques.

Modified:
    llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td
    llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td
    llvm/trunk/test/MC/RISCV/compress-rv32i.s
    llvm/trunk/test/MC/RISCV/rv32c-valid.s
    llvm/trunk/test/MC/RISCV/rv32i-valid.s

Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td?rev=347988&r1=347987&r2=347988&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td Fri Nov 30 05:39:17 2018
@@ -403,6 +403,15 @@ def EBREAK : RVInstI<0b000, OPC_SYSTEM,
   let rd = 0;
   let imm12 = 1;
 }
+
+// This is a de facto standard (as set by GNU binutils) 32-bit unimplemented
+// instruction (i.e., it should always trap, if your implementation has invalid
+// instruction traps).
+def UNIMP : RVInstI<0b001, OPC_SYSTEM, (outs), (ins), "unimp", ""> {
+  let rs1 = 0;
+  let rd = 0;
+  let imm12 = 0b110000000000;
+}
 } // hasSideEffects = 1, mayLoad = 0, mayStore = 0
 
 def CSRRW : CSR_ir<0b001, "csrrw">;

Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td?rev=347988&r1=347987&r2=347988&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td Fri Nov 30 05:39:17 2018
@@ -514,6 +514,13 @@ def C_SDSP : CStackStore<0b111, "c.sdsp"
   let Inst{9-7}   = imm{8-6};
 }
 
+// The all zeros pattern isn't a valid RISC-V instruction. It's used by GNU
+// binutils as 16-bit instruction known to be unimplemented (i.e., trapping).
+let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
+def C_UNIMP : RVInst16<(outs), (ins), "c.unimp", "", [], InstFormatOther> {
+  let Inst{15-0} = 0;
+}
+
 } // Predicates = [HasStdExtC]
 
 //===----------------------------------------------------------------------===//
@@ -677,6 +684,7 @@ def : CompressPat<(ADD GPRNoX0:$rs1, GPR
 def : CompressPat<(ADDI GPRNoX0:$rs1, GPRNoX0:$rs2, 0),
                   (C_MV GPRNoX0:$rs1, GPRNoX0:$rs2)>;
 def : CompressPat<(EBREAK), (C_EBREAK)>;
+def : CompressPat<(UNIMP), (C_UNIMP)>;
 def : CompressPat<(JALR X1, GPRNoX0:$rs1, 0),
                   (C_JALR GPRNoX0:$rs1)>;
 def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2),

Modified: llvm/trunk/test/MC/RISCV/compress-rv32i.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/compress-rv32i.s?rev=347988&r1=347987&r2=347988&view=diff
==============================================================================
--- llvm/trunk/test/MC/RISCV/compress-rv32i.s (original)
+++ llvm/trunk/test/MC/RISCV/compress-rv32i.s Fri Nov 30 05:39:17 2018
@@ -211,3 +211,9 @@ add s0, s0, a5
 # CHECK-INST: c.swsp zero, 252(sp)
 # CHECK: # encoding: [0x82,0xdf]
 sw zero, 252(sp)
+
+# CHECK-BYTES: 00 00
+# CHECK-ALIAS: unimp
+# CHECK-INST: c.unimp
+# CHECK: # encoding: [0x00,0x00]
+unimp

Modified: llvm/trunk/test/MC/RISCV/rv32c-valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/rv32c-valid.s?rev=347988&r1=347987&r2=347988&view=diff
==============================================================================
--- llvm/trunk/test/MC/RISCV/rv32c-valid.s (original)
+++ llvm/trunk/test/MC/RISCV/rv32c-valid.s Fri Nov 30 05:39:17 2018
@@ -103,3 +103,6 @@ c.lui s0, 0xfffe0
 # CHECK-ASM-AND-OBJ: c.lui s0, 1048575
 # CHECK-ASM: encoding: [0x7d,0x74]
 c.lui s0, 0xfffff
+# CHECK-ASM-AND-OBJ: c.unimp
+# CHECK-ASM: encoding: [0x00,0x00]
+c.unimp

Modified: llvm/trunk/test/MC/RISCV/rv32i-valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/rv32i-valid.s?rev=347988&r1=347987&r2=347988&view=diff
==============================================================================
--- llvm/trunk/test/MC/RISCV/rv32i-valid.s (original)
+++ llvm/trunk/test/MC/RISCV/rv32i-valid.s Fri Nov 30 05:39:17 2018
@@ -248,6 +248,9 @@ ecall
 # CHECK-ASM-AND-OBJ: ebreak
 # CHECK-ASM: encoding: [0x73,0x00,0x10,0x00]
 ebreak
+# CHECK-ASM-AND-OBJ: unimp
+# CHECK-ASM: encoding: [0x73,0x10,0x00,0xc0]
+unimp
 
 # CHECK-ASM-AND-OBJ: csrrw t0, 4095, t1
 # CHECK-ASM: encoding: [0xf3,0x12,0xf3,0xff]