[llvm] r347986 - [SelectionDAG] Support result type promotion for FLT_ROUNDS_
Alex Bradbury via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 30 05:18:34 PST 2018
Author: asb
Date: Fri Nov 30 05:18:33 2018
New Revision: 347986
URL: http://llvm.org/viewvc/llvm-project?rev=347986&view=rev
Log:
[SelectionDAG] Support result type promotion for FLT_ROUNDS_
For targets where i32 is not a legal type (e.g. 64-bit RISC-V),
LegalizeIntegerTypes must promote the result of ISD::FLT_ROUNDS_.
Differential Revision: https://reviews.llvm.org/D53820
Added:
llvm/trunk/test/CodeGen/RISCV/flt-rounds.ll
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=347986&r1=347985&r2=347986&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Fri Nov 30 05:18:33 2018
@@ -118,6 +118,8 @@ void DAGTypeLegalizer::PromoteIntegerRes
case ISD::FP_TO_FP16: Res = PromoteIntRes_FP_TO_FP16(N); break;
+ case ISD::FLT_ROUNDS_: Res = PromoteIntRes_FLT_ROUNDS(N); break;
+
case ISD::AND:
case ISD::OR:
case ISD::XOR:
@@ -475,6 +477,13 @@ SDValue DAGTypeLegalizer::PromoteIntRes_
return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
}
+SDValue DAGTypeLegalizer::PromoteIntRes_FLT_ROUNDS(SDNode *N) {
+ EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
+ SDLoc dl(N);
+
+ return DAG.getNode(N->getOpcode(), dl, NVT);
+}
+
SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
SDLoc dl(N);
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=347986&r1=347985&r2=347986&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Fri Nov 30 05:18:33 2018
@@ -345,6 +345,7 @@ private:
SDValue PromoteIntRes_VAARG(SDNode *N);
SDValue PromoteIntRes_XMULO(SDNode *N, unsigned ResNo);
SDValue PromoteIntRes_ADDSUBSAT(SDNode *N);
+ SDValue PromoteIntRes_FLT_ROUNDS(SDNode *N);
// Integer Operand Promotion.
bool PromoteIntegerOperand(SDNode *N, unsigned OpNo);
Added: llvm/trunk/test/CodeGen/RISCV/flt-rounds.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/flt-rounds.ll?rev=347986&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/flt-rounds.ll (added)
+++ llvm/trunk/test/CodeGen/RISCV/flt-rounds.ll Fri Nov 30 05:18:33 2018
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64I %s
+
+declare i32 @llvm.flt.rounds()
+
+define i32 @test_flt_rounds() nounwind {
+; RV32I-LABEL: test_flt_rounds:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi a0, zero, 1
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_flt_rounds:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi a0, zero, 1
+; RV64I-NEXT: ret
+ %1 = call i32 @llvm.flt.rounds()
+ ret i32 %1
+}
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