[llvm] r347227 - [SelectionDAG] simplify vector select with undef operand(s)
Jordan Rupprecht via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 28 13:25:54 PST 2018
Sure; attached the IR repro.
On Wed, Nov 28, 2018 at 1:19 PM Sanjay Patel <spatel at rotateright.com> wrote:
> Can you post the IR for that example using '-S -emit-llvm'?
>
> On Wed, Nov 28, 2018 at 1:58 PM Jordan Rupprecht <rupprecht at google.com>
> wrote:
>
>> Looks like this is causing llvm to crash with msan + opt. Here's a test
>> case courtesy of creduce:
>>
>> $ cat repro.cc
>> float a, b, c, d, e;
>> void f(float *j, float *k) {
>> float g(a ? b * (1.0f - c) : b * (1.0f + c));
>> float h(a ? (1.0f - b) * (1.0f + c) : (1.0f - b) * c);
>> *j = g * 0;
>> *k = h * 0;
>> }
>> float *i;
>> void l() {
>> float m = 0, n = 0;
>> f(&d, &e);
>> m *= d;
>> n *= e;
>> i[0] = i[1] = m;
>> i[2] = i[3] = n;
>> }
>>
>> $ ~/path/to/clang++ -fsanitize=memory -msse4.2 -O2 -c repro.cc
>> fatal error: error in backend: Cannot select: t389: v2i64 = bitcast t388
>> t388: v4i32 = X86ISD::PSHUFD t387, Constant:i8<68>
>> t387: v4i32 = bitcast t266
>> t266: v2i64 = scalar_to_vector t216
>> t216: i64,ch = load<(load 4 from `i32* inttoptr (i64 xor (i64
>> ptrtoint (float* @c to i64), i64 87960930222080) to i32*)`), anyext from
>> i32> t0, t20, undef:i64
>> t20: i64 = xor t317, Constant:i64<87960930222080>
>> t317: i64 = X86ISD::Wrapper TargetGlobalAddress:i64<float*
>> @c> 0
>> t316: i64 = TargetGlobalAddress<float* @c> 0
>> t5: i64 = Constant<87960930222080>
>> t3: i64 = undef
>> t361: i8 = Constant<68>
>> In function: _Z1lv
>> clang-8: error: clang frontend command failed with exit code 70 (use -v
>> to see invocation)
>> clang version 8.0.0 (trunk 347216) (llvm/trunk 347227)
>>
>> On Mon, Nov 19, 2018 at 9:08 AM Sanjay Patel via llvm-commits <
>> llvm-commits at lists.llvm.org> wrote:
>>
>>> Author: spatel
>>> Date: Mon Nov 19 09:06:05 2018
>>> New Revision: 347227
>>>
>>> URL: http://llvm.org/viewvc/llvm-project?rev=347227&view=rev
>>> Log:
>>> [SelectionDAG] simplify vector select with undef operand(s)
>>>
>>> Modified:
>>> llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>>> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
>>> llvm/trunk/test/CodeGen/X86/pr30284.ll
>>> llvm/trunk/test/CodeGen/X86/pr37499.ll
>>>
>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>>> URL:
>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=347227&r1=347226&r2=347227&view=diff
>>>
>>> ==============================================================================
>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Nov 19
>>> 09:06:05 2018
>>> @@ -7816,9 +7816,8 @@ SDValue DAGCombiner::visitVSELECT(SDNode
>>> SDValue N2 = N->getOperand(2);
>>> SDLoc DL(N);
>>>
>>> - // fold (vselect C, X, X) -> X
>>> - if (N1 == N2)
>>> - return N1;
>>> + if (SDValue V = DAG.simplifySelect(N0, N1, N2))
>>> + return V;
>>>
>>> // Canonicalize integer abs.
>>> // vselect (setg[te] X, 0), X, -X ->
>>>
>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
>>> URL:
>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=347227&r1=347226&r2=347227&view=diff
>>>
>>> ==============================================================================
>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Nov 19
>>> 09:06:05 2018
>>> @@ -5078,6 +5078,7 @@ SDValue SelectionDAG::getNode(unsigned O
>>> break;
>>> }
>>> case ISD::SELECT:
>>> + case ISD::VSELECT:
>>> if (SDValue V = simplifySelect(N1, N2, N3))
>>> return V;
>>> break;
>>> @@ -6790,11 +6791,18 @@ SDValue SelectionDAG::simplifySelect(SDV
>>> if (F.isUndef())
>>> return T;
>>>
>>> - // fold (select true, T, F) -> T
>>> - // fold (select false, T, F) -> F
>>> + // select true, T, F --> T
>>> + // select false, T, F --> F
>>> if (auto *CondC = dyn_cast<ConstantSDNode>(Cond))
>>> return CondC->isNullValue() ? F : T;
>>>
>>> + // TODO: This should simplify VSELECT with constant condition using
>>> something
>>> + // like this (but check boolean contents to be complete?):
>>> + // if (ISD::isBuildVectorAllOnes(Cond.getNode()))
>>> + // return T;
>>> + // if (ISD::isBuildVectorAllZeros(Cond.getNode()))
>>> + // return F;
>>> +
>>> // select ?, T, T --> T
>>> if (T == F)
>>> return T;
>>>
>>> Modified: llvm/trunk/test/CodeGen/X86/pr30284.ll
>>> URL:
>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr30284.ll?rev=347227&r1=347226&r2=347227&view=diff
>>>
>>> ==============================================================================
>>> --- llvm/trunk/test/CodeGen/X86/pr30284.ll (original)
>>> +++ llvm/trunk/test/CodeGen/X86/pr30284.ll Mon Nov 19 09:06:05 2018
>>> @@ -4,14 +4,6 @@
>>> define void @undef_cond() {
>>> ; CHECK-LABEL: undef_cond:
>>> ; CHECK: # %bb.0:
>>> -; CHECK-NEXT: vmovapd 0, %zmm0
>>> -; CHECK-NEXT: vmovapd 64, %zmm1
>>> -; CHECK-NEXT: vmovapd {{.*#+}} zmm2 =
>>> [0,16,0,16,0,16,0,16,0,16,0,16,0,16,0,16]
>>> -; CHECK-NEXT: vorpd %zmm2, %zmm0, %zmm0 {%k1}
>>> -; CHECK-NEXT: vorpd %zmm2, %zmm1, %zmm1 {%k1}
>>> -; CHECK-NEXT: vmovapd %zmm1, 64
>>> -; CHECK-NEXT: vmovapd %zmm0, 0
>>> -; CHECK-NEXT: vzeroupper
>>> ; CHECK-NEXT: retl
>>> %a_load22 = load <16 x i64>, <16 x i64>* null, align 1
>>> %bitop = or <16 x i64> %a_load22, <i64 68719476736, i64 68719476736,
>>> i64 68719476736, i64 68719476736, i64 68719476736, i64 68719476736, i64
>>> 68719476736, i64 68719476736, i64 68719476736, i64 68719476736, i64
>>> 68719476736, i64 68719476736, i64 68719476736, i64 68719476736, i64
>>> 68719476736, i64 68719476736>
>>>
>>> Modified: llvm/trunk/test/CodeGen/X86/pr37499.ll
>>> URL:
>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr37499.ll?rev=347227&r1=347226&r2=347227&view=diff
>>>
>>> ==============================================================================
>>> --- llvm/trunk/test/CodeGen/X86/pr37499.ll (original)
>>> +++ llvm/trunk/test/CodeGen/X86/pr37499.ll Mon Nov 19 09:06:05 2018
>>> @@ -4,14 +4,7 @@
>>> define <2 x i64> @undef_tval() {
>>> ; CHECK-LABEL: undef_tval:
>>> ; CHECK: # %bb.0:
>>> -; CHECK-NEXT: vmovdqa {{.*#+}} xmm0 = [1,1,1,1,1,1,1,1]
>>> -; CHECK-NEXT: movb $1, %al
>>> -; CHECK-NEXT: kmovw %eax, %k1
>>> -; CHECK-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
>>> -; CHECK-NEXT: vmovdqa32 %ymm1, %ymm1 {%k1} {z}
>>> -; CHECK-NEXT: vpmovdw %ymm1, %xmm1
>>> -; CHECK-NEXT: vpblendvb %xmm1, %xmm0, %xmm0, %xmm0
>>> -; CHECK-NEXT: vzeroupper
>>> +; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = [1,1,1,1,1,1,1,1]
>>> ; CHECK-NEXT: retq
>>> %1 = tail call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64>
>>> undef, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>,
>>> i8 1) #3
>>> %2 = bitcast <8 x i16> %1 to <2 x i64>
>>>
>>>
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>>
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