[PATCH] D54957: [llvm-mca][MC] Add the ability to declare which processor resources model load/store queues (PR36666).

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb updated this revision to Diff 175728.
andreadb added a comment.

Address review comments.

Raised PR39828, PR39829 and PR39830.
Added references to those upstream bugzillas in code comments as suggested by Roman.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D54957/new/

https://reviews.llvm.org/D54957

Files:
  include/llvm/MC/MCSchedule.h
  include/llvm/Target/TargetSchedule.td
  lib/Target/X86/X86ScheduleBdVer2.td
  test/tools/llvm-mca/X86/BdVer2/load-throughput.s
  test/tools/llvm-mca/X86/BdVer2/store-throughput.s
  tools/llvm-mca/Views/SchedulerStatistics.cpp
  tools/llvm-mca/Views/SchedulerStatistics.h
  tools/llvm-mca/include/HardwareUnits/LSUnit.h
  tools/llvm-mca/lib/Context.cpp
  tools/llvm-mca/lib/HardwareUnits/LSUnit.cpp
  tools/llvm-mca/llvm-mca.cpp
  utils/TableGen/CodeGenSchedule.cpp
  utils/TableGen/CodeGenSchedule.h
  utils/TableGen/SubtargetEmitter.cpp

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D54957.175728.patch
Type: text/x-patch
Size: 39697 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20181128/2c470b28/attachment.bin>