[PATCH] D54882: [AMDGPU] Add sdwa support for ADD|SUB U64 decomposed Pseudos

[Ron Lieberman via Phabricator via llvm-commits]

ronlieb added a comment.

In D54882#1309711 <https://reviews.llvm.org/D54882#1309711>, @rampitec wrote:

> In D54882#1309708 <https://reviews.llvm.org/D54882#1309708>, @ronlieb wrote:
>
> > Adding the shrink pass just before Peephole SDWA does not help the lit test,  it made no difference.
> >  I think at this point i should proceed with adding the MIR test to verify when we cannot fold.
>
>
> Do you know why was it unable to shrink these instructions?


SIInstrInfo::splitScalar64BitAddSub converts the S_ADD_U64_PSEUDO into the two  add instructions which use the SReg_64_XEXECRegClass instead of VCC.
Later when SIShrinkInstructions::runOnMachineFunction pass runs, it sees that the Carry regs are not VCC and simply marks them with a hint to later convert to VCC ,
and then continues without doing a transformation.

  if (SDst) {
    if (SDst->getReg() != AMDGPU::VCC) {
      if (TargetRegisterInfo::isVirtualRegister(SDst->getReg()))
        MRI.setRegAllocationHint(SDst->getReg(), 0, AMDGPU::VCC);
      continue;
    }
  
    // All of the instructions with carry outs also have an SGPR input in
    // src2.
    if (Src2 && Src2->getReg() != AMDGPU::VCC) {
      if (TargetRegisterInfo::isVirtualRegister(Src2->getReg()))
        MRI.setRegAllocationHint(Src2->getReg(), 0, AMDGPU::VCC);
  
      continue;
    }
  }


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D54882/new/

https://reviews.llvm.org/D54882