[PATCH] D50977: [TableGen] Examine entire subreg compositions to detect ambiguity

[Ulrich Weigand via Phabricator via llvm-commits]

uweigand added a comment.

I must have missed the earlier discussion, but I agree with @bjope 's comment earlier that subreg_h32(V0) -> F0S is actually wrong; there should not be any subreg_h32(V0) at all!

For 128-bit registers, I understood that subreg_h32(Reg) should be inherited as subreg_h32(subreg_l64(Reg)), but there is no actual subreg_l64 of V registers.

Can you explain why tablegen comes up with that implicit definition?   Is this because V registers have a subreg_h64 as first and only subreg?

If so, maybe we can fix this by swapping around the low and high subregs of all other register definitions, so that then subreg_h32 *always* maps to subreg_h32(subreg_h64)), and instead of explicit subreg_hh32 and subreg_hl32 we have rather subreg_lh32 and subreg_ll32 ?


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https://reviews.llvm.org/D50977