[PATCH] D54836: [X86] Add DAG combine to combine a v8i32->v8i16 truncate with a packuswb that truncates v8i16->v8i8.

[Craig Topper via Phabricator via llvm-commits]

craig.topper marked an inline comment as done.
craig.topper added inline comments.


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Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:9082
 
+  // If we have (AssertZext (truncate (AssertSext X, iX)), iY) and Y is smaller
+  // than X. Just move the AssertZext in front of the truncate and drop the
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I wonder if we could just float all Asserts above truncates? And more aggressively merge adjacent asserts?


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https://reviews.llvm.org/D54836