[llvm] r347599 - [AArch64] Refactor the scheduling predicates (3/3) (NFC)
Evandro Menezes via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 26 13:47:47 PST 2018
Author: evandro
Date: Mon Nov 26 13:47:46 2018
New Revision: 347599
URL: http://llvm.org/viewvc/llvm-project?rev=347599&view=rev
Log:
[AArch64] Refactor the scheduling predicates (3/3) (NFC)
Refactor the scheduling predicates based on `MCInstPredicate`. In this
case, `AArch64InstrInfo::hasExtendedReg()`.
Differential revision: https://reviews.llvm.org/D54822
Modified:
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h
llvm/trunk/lib/Target/AArch64/AArch64SchedPredicates.td
llvm/trunk/lib/Target/AArch64/AArch64Schedule.td
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp?rev=347599&r1=347598&r2=347599&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp Mon Nov 26 13:47:46 2018
@@ -1740,33 +1740,6 @@ bool AArch64InstrInfo::expandPostRAPseud
return true;
}
-/// Return true if this is this instruction has a non-zero immediate
-bool AArch64InstrInfo::hasExtendedReg(const MachineInstr &MI) {
- switch (MI.getOpcode()) {
- default:
- break;
- case AArch64::ADDSWrx:
- case AArch64::ADDSXrx:
- case AArch64::ADDSXrx64:
- case AArch64::ADDWrx:
- case AArch64::ADDXrx:
- case AArch64::ADDXrx64:
- case AArch64::SUBSWrx:
- case AArch64::SUBSXrx:
- case AArch64::SUBSXrx64:
- case AArch64::SUBWrx:
- case AArch64::SUBXrx:
- case AArch64::SUBXrx64:
- if (MI.getOperand(3).isImm()) {
- unsigned val = MI.getOperand(3).getImm();
- return (val != 0);
- }
- break;
- }
-
- return false;
-}
-
// Return true if this instruction simply sets its single destination register
// to zero. This is equivalent to a register rename of the zero-register.
bool AArch64InstrInfo::isGPRZero(const MachineInstr &MI) {
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h?rev=347599&r1=347598&r2=347599&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h Mon Nov 26 13:47:46 2018
@@ -62,10 +62,6 @@ public:
unsigned isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;
- /// Returns true if there is an extendable register and that the extending
- /// value is non-zero.
- static bool hasExtendedReg(const MachineInstr &MI);
-
/// Does this instruction set its full destination register to zero?
static bool isGPRZero(const MachineInstr &MI);
Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedPredicates.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedPredicates.td?rev=347599&r1=347598&r2=347599&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedPredicates.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedPredicates.td Mon Nov 26 13:47:46 2018
@@ -28,6 +28,10 @@ def CheckMemScaled : CheckImmOperandSim
// Generic predicates.
+// Identify arithmetic instructions with extend.
+def IsArithExtPred : CheckOpcode<[ADDWrx, ADDXrx, ADDXrx64, ADDSWrx, ADDSXrx, ADDSXrx64,
+ SUBWrx, SUBXrx, SUBXrx64, SUBSWrx, SUBSXrx, SUBSXrx64]>;
+
// Identify arithmetic instructions with shift.
def IsArithShiftPred : CheckOpcode<[ADDWrs, ADDXrs, ADDSWrs, ADDSXrs,
SUBWrs, SUBXrs, SUBSWrs, SUBSXrs]>;
@@ -71,25 +75,34 @@ def IsStoreRegOffsetPred : CheckOpcode<
// Target predicates.
-// Identify arithmetic and logic instructions with a shifted register.
-def RegShiftedFn : TIIPredicate<"hasShiftedReg",
- MCOpcodeSwitchStatement<
- [MCOpcodeSwitchCase<
- !listconcat(IsArithShiftPred.ValidOpcodes,
- IsLogicShiftPred.ValidOpcodes),
+// Identify arithmetic instructions with an extended register.
+def RegExtendedFn : TIIPredicate<"hasExtendedReg",
+ MCOpcodeSwitchStatement<
+ [MCOpcodeSwitchCase<
+ IsArithExtPred.ValidOpcodes,
MCReturnStatement<CheckNot<CheckZeroOperand<3>>>>],
- MCReturnStatement<FalsePred>>>;
-def RegShiftedPred : MCSchedPredicate<RegShiftedFn>;
+ MCReturnStatement<FalsePred>>>;
+def RegExtendedPred : MCSchedPredicate<RegExtendedFn>;
+
+// Identify arithmetic and logic instructions with a shifted register.
+def RegShiftedFn : TIIPredicate<"hasShiftedReg",
+ MCOpcodeSwitchStatement<
+ [MCOpcodeSwitchCase<
+ !listconcat(IsArithShiftPred.ValidOpcodes,
+ IsLogicShiftPred.ValidOpcodes),
+ MCReturnStatement<CheckNot<CheckZeroOperand<3>>>>],
+ MCReturnStatement<FalsePred>>>;
+def RegShiftedPred : MCSchedPredicate<RegShiftedFn>;
// Identify a load or store using the register offset addressing mode
// with an extended or scaled register.
-def ScaledIdxFn : TIIPredicate<"isScaledAddr",
- MCOpcodeSwitchStatement<
- [MCOpcodeSwitchCase<
- !listconcat(IsLoadRegOffsetPred.ValidOpcodes,
- IsStoreRegOffsetPred.ValidOpcodes),
- MCReturnStatement<
- CheckAny<[CheckNot<CheckMemExtLSL>,
- CheckMemScaled]>>>],
- MCReturnStatement<FalsePred>>>;
-def ScaledIdxPred : MCSchedPredicate<ScaledIdxFn>;
+def ScaledIdxFn : TIIPredicate<"isScaledAddr",
+ MCOpcodeSwitchStatement<
+ [MCOpcodeSwitchCase<
+ !listconcat(IsLoadRegOffsetPred.ValidOpcodes,
+ IsStoreRegOffsetPred.ValidOpcodes),
+ MCReturnStatement<
+ CheckAny<[CheckNot<CheckMemExtLSL>,
+ CheckMemScaled]>>>],
+ MCReturnStatement<FalsePred>>>;
+def ScaledIdxPred : MCSchedPredicate<ScaledIdxFn>;
Modified: llvm/trunk/lib/Target/AArch64/AArch64Schedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Schedule.td?rev=347599&r1=347598&r2=347599&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64Schedule.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64Schedule.td Mon Nov 26 13:47:46 2018
@@ -50,9 +50,6 @@ def WriteLDIdx : SchedWrite; // Load fro
def WriteSTIdx : SchedWrite; // Store to a register index (maybe scaled).
def ReadAdrBase : SchedRead; // Read the base resister of a reg-offset LD/ST.
-// Predicate for determining when a extendedable register is extended.
-def RegExtendedPred : SchedPredicate<[{TII->hasExtendedReg(*MI)}]>;
-
// Serialized two-level address load.
// EXAMPLE: LOADGot
def WriteLDAdr : WriteSequence<[WriteAdr, WriteLD]>;
More information about the llvm-commits
mailing list