[PATCH] D54907: [PPC64] Support toc-optimization for '@got' relocations
Sean Fertile via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 26 10:08:04 PST 2018
sfertile created this revision.
sfertile added reviewers: syzaara, ruiu, MaskRay, rdhindsa.
Herald added subscribers: jsji, kbarton, arichardson, nemanjai, emaste.
Herald added a reviewer: espindola.
Extends the toc-optimizations to the '@got' relocations.
Repository:
rLLD LLVM Linker
https://reviews.llvm.org/D54907
Files:
ELF/Arch/PPC64.cpp
test/ELF/ppc64-got-off.s
Index: test/ELF/ppc64-got-off.s
===================================================================
--- test/ELF/ppc64-got-off.s
+++ test/ELF/ppc64-got-off.s
@@ -8,6 +8,14 @@
# RUN: ld.lld -shared --no-toc-optimize %t.o -o %t
# RUN: llvm-objdump -d %t | FileCheck %s
+# RUN: llvm-mc -filetype=obj -triple=powerpc64le-unknown-linux %s -o %t.o
+# RUN: ld.lld -shared %t.o -o %t
+# RUN: llvm-objdump -d %t | FileCheck --check-prefix=OPT %s
+
+# RUN: llvm-mc -filetype=obj -triple=powerpc64-unknown-linux %s -o %t.o
+# RUN: ld.lld -shared %t.o -o %t
+# RUN: llvm-objdump -d %t | FileCheck --check-prefix=OPT %s
+
.abiversion 2
.section ".text"
@@ -38,6 +46,15 @@
# CHECK-NEXT: li 6, 0
# CHECK-NEXT: ori 6, 6, 32776
+# OPT-LABEL: func
+# OPT: nop
+# OPT-NEXT: ld 3, -32760(2)
+# OPT-NEXT: ld 4, -32760(2)
+# OPT-NEXT: lis 5, -1
+# OPT-NEXT: ori 5, 5, 32776
+# OPT-NEXT: li 6, 0
+# OPT-NEXT: ori 6, 6, 32776
+
# Since the got entry for a is .got[1] and the TOC base points to
# .got + 0x8000, the offset for a at got is -0x7FF8 --> -32760
Index: ELF/Arch/PPC64.cpp
===================================================================
--- ELF/Arch/PPC64.cpp
+++ ELF/Arch/PPC64.cpp
@@ -596,15 +596,23 @@
}
}
-static bool isTocRelType(RelType Type) {
- return Type == R_PPC64_TOC16_HA || Type == R_PPC64_TOC16_LO_DS ||
- Type == R_PPC64_TOC16_LO;
+static bool isTocOptType(RelType Type) {
+ switch (Type) {
+ case R_PPC64_GOT16_HA:
+ case R_PPC64_GOT16_LO_DS:
+ case R_PPC64_TOC16_HA:
+ case R_PPC64_TOC16_LO_DS:
+ case R_PPC64_TOC16_LO:
+ return true;
+ default:
+ return false;
+ }
}
void PPC64::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
// We need to save the original relocation type to determine if we should
// toc-optimize the instructions being relocated.
- bool IsTocRelType = isTocRelType(Type);
+ bool ShouldTocOptimize = isTocOptType(Type);
// For TOC-relative and GOT-indirect relocations, proceed in terms of the
// corresponding ADDR16 relocation type.
std::tie(Type, Val) = toAddr16Rel(Type, Val);
@@ -634,7 +642,7 @@
case R_PPC64_ADDR16_HA:
case R_PPC64_REL16_HA:
case R_PPC64_TPREL16_HA:
- if (Config->TocOptimize && IsTocRelType && ha(Val) == 0)
+ if (Config->TocOptimize && ShouldTocOptimize && ha(Val) == 0)
writeInstrFromHalf16(Loc, 0x60000000);
else
write16(Loc, ha(Val));
@@ -666,7 +674,7 @@
// When the high-adjusted part of a toc relocation evalutes to 0, it is
// changed into a nop. The lo part then needs to be updated to use the
// toc-pointer register r2, as the base register.
- if (Config->TocOptimize && IsTocRelType && ha(Val) == 0) {
+ if (Config->TocOptimize && ShouldTocOptimize && ha(Val) == 0) {
uint32_t Instr = readInstrFromHalf16(Loc);
if (isInstructionUpdateForm(Instr))
error(getErrorLocation(Loc) +
@@ -684,7 +692,7 @@
uint32_t Inst = readInstrFromHalf16(Loc);
uint16_t Mask = isDQFormInstruction(Inst) ? 0xF : 0x3;
checkAlignment(Loc, lo(Val), Mask + 1, Type);
- if (Config->TocOptimize && IsTocRelType && ha(Val) == 0) {
+ if (Config->TocOptimize && ShouldTocOptimize && ha(Val) == 0) {
// When the high-adjusted part of a toc relocation evalutes to 0, it is
// changed into a nop. The lo part then needs to be updated to use the toc
// pointer register r2, as the base register.
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