[PATCH] D54822: [AArch64] Refactor the scheduling predicates (3/3) (NFC)
Evandro Menezes via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 23 14:55:18 PST 2018
evandro marked 4 inline comments as done.
evandro added inline comments.
================
Comment at: llvm/lib/Target/AArch64/AArch64SchedPredicates.td:78-83
+// Identify arithmetic instructions with an extended register.
+def RegExtendedBody : CheckAll<[IsArithExtPred,
+ CheckNot<CheckZeroOperand<3>>]>;
+def RegExtendedPred : MCSchedPredicate<RegExtendedBody>;
+def RegExtendedFn : TIIPredicate<"hasExtendedReg",
+ MCReturnStatement<RegExtendedBody>>;
----------------
andreadb wrote:
> You should just use a MCOpcodeSwitchStatement.
Again, `IsArithExtPred` should be reused in an upcoming patch.
Repository:
rL LLVM
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D54822/new/
https://reviews.llvm.org/D54822
More information about the llvm-commits
mailing list