[PATCH] D54820: [AArch64] Refactor the scheduling predicates (2/3) (NFC)

[Evandro Menezes via Phabricator via llvm-commits]

evandro marked 2 inline comments as done.
evandro added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64SchedPredicates.td:74-79
+// Identify arithmetic and logic instructions with a shifted register.
+def RegShiftedBody : CheckAll<[IsArithLogicShiftPred,
+                               CheckNot<CheckZeroOperand<3>>]>;
+def RegShiftedPred : MCSchedPredicate<RegShiftedBody>;
+def RegShiftedFn   : TIIPredicate<"hasShiftedReg",
+                                  MCReturnStatement<RegShiftedBody>>;
----------------
andreadb wrote:
> Same as D54833 and D54777.
> 
> ```
> def RegShiftedPred : MCSchedPredicate<RegShiftedBody>;
> ```
> 
> You are inlining the entire body of `hasShiftedReg` here. You should replace it with this:
> 
> ```
> def RegShiftedPred : MCSchedPredicate<RegShiftedFn>;
> ```
> 
> A TIIPredicate is a special kind of MCInstPredicate. See my other comment in D54777.
> 
> You should also rewrite `RegShiftedFn` so that it uses a more readable `MCOpcodeSwitchStatement`.
Again, I intend to reuse `IsArithLogicShiftPred` in another patch.


Repository:
  rL LLVM

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  https://reviews.llvm.org/D54820/new/

https://reviews.llvm.org/D54820