[llvm] r347478 - [DAGCombiner] form 'not' ops ahead of shifts (PR39657)
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 23 13:36:55 PST 2018
https://reviews.llvm.org/rL347502
On Fri, Nov 23, 2018 at 7:48 AM Sanjay Patel <spatel at rotateright.com> wrote:
> That's correct - unless something in the DAG is unknowingly creating a
> shift with an oversized shift constant, this won't be a problem. We fold
> any IR in this form to 'undef' in InstSimplify.
>
> I'll prepare a patch and should have it posted by end-of-day today. :)
>
> On Fri, Nov 23, 2018 at 7:15 AM Mikael Holmén <mikael.holmen at ericsson.com>
> wrote:
>
>>
>>
>> On 11/23/18 2:54 PM, Sanjay Patel wrote:
>> > Thanks - if this is a blocker, feel free to revert.
>> >
>>
>> We stumbled on it in fuzz testing so I don't think it's a blocker.
>>
>> I suppose a too big shift count is needed for it to trigger, so no
>> "proper" code should suffer from this?
>>
>> So it's no panic atm (I'll get back if it turns out it is) but it would
>> of course be nice if you'd fix it at some point.
>>
>> Thanks,
>> Mikael
>>
>> > We're missing all of the obvious shift simplifications at DAG node
>> > creation time. Those are just in the DAGCombiner. So if we process some
>> > other node before the bogus shift, we have this danger.
>> >
>> > The solution will be similar to:
>> > https://reviews.llvm.org/rL347210
>> >
>> > We should be simplifying all shift nodes like this before they are ever
>> > created.
>> >
>> > On Fri, Nov 23, 2018 at 6:15 AM Mikael Holmén
>> > <mikael.holmen at ericsson.com <mailto:mikael.holmen at ericsson.com>> wrote:
>> >
>> > Hi Sanjay,
>> >
>> > The following:
>> >
>> > llc -o - bbi-21386.ll
>> >
>> > hits an assertion with this commit:
>> >
>> > .text
>> > .file "bbi-21386.ll"
>> > llc: ../include/llvm/ADT/APInt.h:979: void
>> > llvm::APInt::lshrInPlace(unsigned int): Assertion `ShiftAmt <=
>> BitWidth
>> > && "Invalid shift amount"' failed.
>> > Stack dump:
>> > 0. Program arguments: build-all/bin/llc -o - bbi-21386.ll
>> > 1. Running pass 'Function Pass Manager' on module
>> 'bbi-21386.ll'.
>> > 2. Running pass 'X86 DAG->DAG Instruction Selection' on
>> > function '@f'
>> > #0 0x0000000002180d44 PrintStackTraceSignalHandler(void*)
>> > (build-all/bin/llc+0x2180d44)
>> > #1 0x000000000217ee70 llvm::sys::RunSignalHandlers()
>> > (build-all/bin/llc+0x217ee70)
>> > #2 0x00000000021810a8 SignalHandler(int)
>> (build-all/bin/llc+0x21810a8)
>> > #3 0x00007f6d61e9f330 __restore_rt
>> > (/lib/x86_64-linux-gnu/libpthread.so.0+0x10330)
>> > #4 0x00007f6d60a8ec37 gsignal
>> >
>> /build/eglibc-ripdx6/eglibc-2.19/signal/../nptl/sysdeps/unix/sysv/linux/raise.c:56:0
>> > #5 0x00007f6d60a92028 abort
>> > /build/eglibc-ripdx6/eglibc-2.19/stdlib/abort.c:91:0
>> > #6 0x00007f6d60a87bf6 __assert_fail_base
>> > /build/eglibc-ripdx6/eglibc-2.19/assert/assert.c:92:0
>> > #7 0x00007f6d60a87ca2 (/lib/x86_64-linux-gnu/libc.so.6+0x2fca2)
>> > #8 0x0000000001ee1491 (anonymous
>> > namespace)::DAGCombiner::visitXOR(llvm::SDNode*)
>> > (build-all/bin/llc+0x1ee1491)
>> > #9 0x0000000001eabdd2 (anonymous
>> > namespace)::DAGCombiner::visit(llvm::SDNode*)
>> > (build-all/bin/llc+0x1eabdd2)
>> > #10 0x0000000001ea876c (anonymous
>> > namespace)::DAGCombiner::combine(llvm::SDNode*)
>> > (build-all/bin/llc+0x1ea876c)
>> > #11 0x0000000001ea7f48
>> llvm::SelectionDAG::Combine(llvm::CombineLevel,
>> > llvm::AAResults*, llvm::CodeGenOpt::Level)
>> (build-all/bin/llc+0x1ea7f48)
>> > #12 0x000000000203384a llvm::SelectionDAGISel::CodeGenAndEmitDAG()
>> > (build-all/bin/llc+0x203384a)
>> > #13 0x0000000002031d23
>> > llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function const&)
>> > (build-all/bin/llc+0x2031d23)
>> > #14 0x000000000202de9c
>> > llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&)
>> > (build-all/bin/llc+0x202de9c)
>> > #15 0x00000000012d5eee (anonymous
>> >
>> namespace)::X86DAGToDAGISel::runOnMachineFunction(llvm::MachineFunction&)
>> >
>> > (build-all/bin/llc+0x12d5eee)
>> > #16 0x000000000184af0d
>> > llvm::MachineFunctionPass::runOnFunction(llvm::Function&)
>> > (build-all/bin/llc+0x184af0d)
>> > #17 0x0000000001b8939d
>> > llvm::FPPassManager::runOnFunction(llvm::Function&)
>> > (build-all/bin/llc+0x1b8939d)
>> > #18 0x0000000001b89658
>> llvm::FPPassManager::runOnModule(llvm::Module&)
>> > (build-all/bin/llc+0x1b89658)
>> > #19 0x0000000001b89aba
>> > llvm::legacy::PassManagerImpl::run(llvm::Module&)
>> > (build-all/bin/llc+0x1b89aba)
>> > #20 0x0000000000726be5 compileModule(char**, llvm::LLVMContext&)
>> > (build-all/bin/llc+0x726be5)
>> > #21 0x0000000000724330 main (build-all/bin/llc+0x724330)
>> > #22 0x00007f6d60a79f45 __libc_start_main
>> > /build/eglibc-ripdx6/eglibc-2.19/csu/libc-start.c:321:0
>> > #23 0x00000000007223aa _start (build-all/bin/llc+0x7223aa)
>> > Abort
>> >
>> > I know the input shift is UB but
>> >
>> > %shr = lshr i32 %a, 33
>> >
>> > but shouldn't crash anyway.
>> >
>> > /Mikael
>> >
>> > On 11/22/18 8:24 PM, Sanjay Patel via llvm-commits wrote:
>> > > Author: spatel
>> > > Date: Thu Nov 22 11:24:10 2018
>> > > New Revision: 347478
>> > >
>> > > URL: http://llvm.org/viewvc/llvm-project?rev=347478&view=rev
>> > > Log:
>> > > [DAGCombiner] form 'not' ops ahead of shifts (PR39657)
>> > >
>> > > We fail to canonicalize IR this way (prefer 'not' ops to
>> > arbitrary 'xor'),
>> > > but that would not matter without this patch because DAGCombiner
>> was
>> > > reversing that transform. I think we need this transform in the
>> > backend
>> > > regardless of what happens in IR to catch cases where the
>> shift-xor
>> > > is formed late from GEP or other ops.
>> > >
>> > > https://rise4fun.com/Alive/NC1
>> > >
>> > > Name: shl
>> > > Pre: (-1 << C2) == C1
>> > > %shl = shl i8 %x, C2
>> > > %r = xor i8 %shl, C1
>> > > =>
>> > > %not = xor i8 %x, -1
>> > > %r = shl i8 %not, C2
>> > >
>> > > Name: shr
>> > > Pre: (-1 u>> C2) == C1
>> > > %sh = lshr i8 %x, C2
>> > > %r = xor i8 %sh, C1
>> > > =>
>> > > %not = xor i8 %x, -1
>> > > %r = lshr i8 %not, C2
>> > >
>> > > https://bugs.llvm.org/show_bug.cgi?id=39657
>> > >
>> > > Modified:
>> > > llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>> > > llvm/trunk/test/CodeGen/AArch64/xor.ll
>> > > llvm/trunk/test/CodeGen/ARM/pr36577.ll
>> > >
>> >
>> llvm/trunk/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
>> > > llvm/trunk/test/CodeGen/PowerPC/setcc-to-sub.ll
>> > > llvm/trunk/test/CodeGen/PowerPC/testComparesigesll.ll
>> > > llvm/trunk/test/CodeGen/PowerPC/testComparesigeuc.ll
>> > > llvm/trunk/test/CodeGen/PowerPC/testComparesigeui.ll
>> > > llvm/trunk/test/CodeGen/PowerPC/testComparesigeus.ll
>> > > llvm/trunk/test/CodeGen/PowerPC/testComparesileuc.ll
>> > > llvm/trunk/test/CodeGen/PowerPC/testComparesileui.ll
>> > > llvm/trunk/test/CodeGen/PowerPC/testComparesileus.ll
>> > > llvm/trunk/test/CodeGen/PowerPC/testComparesllgeuc.ll
>> > > llvm/trunk/test/CodeGen/PowerPC/testComparesllgeui.ll
>> > > llvm/trunk/test/CodeGen/PowerPC/testComparesllgeus.ll
>> > > llvm/trunk/test/CodeGen/PowerPC/testComparesllleuc.ll
>> > > llvm/trunk/test/CodeGen/PowerPC/testComparesllleui.ll
>> > > llvm/trunk/test/CodeGen/PowerPC/testComparesllleus.ll
>> > > llvm/trunk/test/CodeGen/X86/not-and-simplify.ll
>> > > llvm/trunk/test/CodeGen/X86/xor.ll
>> > >
>> > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>> > > URL:
>> >
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=347478&r1=347477&r2=347478&view=diff
>> > >
>> >
>> ==============================================================================
>> > > --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>> (original)
>> > > +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Nov
>> > 22 11:24:10 2018
>> > > @@ -6133,6 +6133,23 @@ SDValue DAGCombiner::visitXOR(SDNode *N)
>> > > return DAG.getNode(ISD::AND, DL, VT, NotX, N1);
>> > > }
>> > >
>> > > + if ((N0Opcode == ISD::SRL || N0Opcode == ISD::SHL) &&
>> > N0.hasOneUse()) {
>> > > + ConstantSDNode *XorC = isConstOrConstSplat(N1);
>> > > + ConstantSDNode *ShiftC =
>> isConstOrConstSplat(N0.getOperand(1));
>> > > + if (XorC && ShiftC) {
>> > > + APInt Ones =
>> APInt::getAllOnesValue(VT.getScalarSizeInBits());
>> > > + Ones = N0Opcode == ISD::SHL ?
>> Ones.shl(ShiftC->getZExtValue())
>> > > + :
>> > Ones.lshr(ShiftC->getZExtValue());
>> > > + if (XorC->getAPIntValue() == Ones) {
>> > > + // If the xor constant is a shifted -1, do a 'not'
>> > before the shift:
>> > > + // xor (X << ShiftC), XorC --> (not X) << ShiftC
>> > > + // xor (X >> ShiftC), XorC --> (not X) >> ShiftC
>> > > + SDValue Not = DAG.getNOT(DL, N0.getOperand(0), VT);
>> > > + return DAG.getNode(N0Opcode, DL, VT, Not,
>> N0.getOperand(1));
>> > > + }
>> > > + }
>> > > + }
>> > > +
>> > > // fold Y = sra (X, size(X)-1); xor (add (X, Y), Y) -> (abs
>> X)
>> > > if (TLI.isOperationLegalOrCustom(ISD::ABS, VT)) {
>> > > SDValue A = N0Opcode == ISD::ADD ? N0 : N1;
>> > > @@ -6196,6 +6213,10 @@ SDValue DAGCombiner::visitXOR(SDNode *N)
>> > > /// Handle transforms common to the three shifts, when the
>> > shift amount is a
>> > > /// constant.
>> > > SDValue DAGCombiner::visitShiftByConstant(SDNode *N,
>> > ConstantSDNode *Amt) {
>> > > + // Do not turn a 'not' into a regular xor.
>> > > + if (isBitwiseNot(N->getOperand(0)))
>> > > + return SDValue();
>> > > +
>> > > SDNode *LHS = N->getOperand(0).getNode();
>> > > if (!LHS->hasOneUse()) return SDValue();
>> > >
>> > >
>> > > Modified: llvm/trunk/test/CodeGen/AArch64/xor.ll
>> > > URL:
>> >
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/xor.ll?rev=347478&r1=347477&r2=347478&view=diff
>> > >
>> >
>> ==============================================================================
>> > > --- llvm/trunk/test/CodeGen/AArch64/xor.ll (original)
>> > > +++ llvm/trunk/test/CodeGen/AArch64/xor.ll Thu Nov 22 11:24:10
>> 2018
>> > > @@ -4,9 +4,8 @@
>> > > define i32 @PR39657(i8* %p, i64 %x) {
>> > > ; CHECK-LABEL: PR39657:
>> > > ; CHECK: // %bb.0:
>> > > -; CHECK-NEXT: lsl x8, x1, #2
>> > > -; CHECK-NEXT: eor x8, x8, #0xfffffffffffffffc
>> > > -; CHECK-NEXT: ldr w0, [x0, x8]
>> > > +; CHECK-NEXT: mvn x8, x1
>> > > +; CHECK-NEXT: ldr w0, [x0, x8, lsl #2]
>> > > ; CHECK-NEXT: ret
>> > > %sh = shl i64 %x, 2
>> > > %mul = xor i64 %sh, -4
>> > >
>> > > Modified: llvm/trunk/test/CodeGen/ARM/pr36577.ll
>> > > URL:
>> >
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/pr36577.ll?rev=347478&r1=347477&r2=347478&view=diff
>> > >
>> >
>> ==============================================================================
>> > > --- llvm/trunk/test/CodeGen/ARM/pr36577.ll (original)
>> > > +++ llvm/trunk/test/CodeGen/ARM/pr36577.ll Thu Nov 22 11:24:10
>> 2018
>> > > @@ -9,12 +9,11 @@
>> > >
>> > > ; CHECK-LABEL: pr36577
>> > > ; CHECK: ldrh r0, [r0]
>> > > -; CHECK: bic r0, r1, r0, lsr #5
>> > > -; CHECK: mvn r1, #7
>> > > -; CHECK: orr r0, r0, r1
>> > > +; CHECK: mvn r0, r0, lsr #7
>> > > +; CHECK: orr r0, r1, r0, lsl #2
>> > > ; CHECK-T2: ldrh r0, [r0]
>> > > -; CHECK-T2: bic.w r0, r1, r0, lsr #5
>> > > -; CHECK-T2: orn r0, r0, #7
>> > > +; CHECK-T2: mvn.w r0, r0, lsr #7
>> > > +; CHECK-T2: orr.w r0, r1, r0, lsl #2
>> > > define dso_local arm_aapcscc i32** @pr36577() {
>> > > entry:
>> > > %0 = load i16, i16* @a, align 2
>> > >
>> > > Modified:
>> >
>> llvm/trunk/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
>> > > URL:
>> >
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll?rev=347478&r1=347477&r2=347478&view=diff
>> > >
>> >
>> ==============================================================================
>> > > ---
>> >
>> llvm/trunk/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
>> (original)
>> > > +++
>> >
>> llvm/trunk/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll Thu
>> > Nov 22 11:24:10 2018
>> > > @@ -147,9 +147,8 @@ define signext i32 @zeroEqualityTest05()
>> > > ; CHECK-NEXT: li 4, -1
>> > > ; CHECK-NEXT: isel 5, 4, 3, 0
>> > > ; CHECK-NEXT: .LBB4_3: # %endblock
>> > > -; CHECK-NEXT: srwi 3, 5, 31
>> > > -; CHECK-NEXT: xori 3, 3, 1
>> > > -; CHECK-NEXT: clrldi 3, 3, 32
>> > > +; CHECK-NEXT: nor 3, 5, 5
>> > > +; CHECK-NEXT: rlwinm 3, 3, 1, 31, 31
>> > > ; CHECK-NEXT: blr
>> > > %call = tail call signext i32 @memcmp(i8* bitcast ([4 x i32]*
>> > @zeroEqualityTest03.buffer1 to i8*), i8* bitcast ([4 x i32]*
>> > @zeroEqualityTest03.buffer2 to i8*), i64 16)
>> > > %call.lobit = lshr i32 %call, 31
>> > >
>> > > Modified: llvm/trunk/test/CodeGen/PowerPC/setcc-to-sub.ll
>> > > URL:
>> >
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/setcc-to-sub.ll?rev=347478&r1=347477&r2=347478&view=diff
>> > >
>> >
>> ==============================================================================
>> > > --- llvm/trunk/test/CodeGen/PowerPC/setcc-to-sub.ll (original)
>> > > +++ llvm/trunk/test/CodeGen/PowerPC/setcc-to-sub.ll Thu Nov 22
>> > 11:24:10 2018
>> > > @@ -36,8 +36,8 @@ define zeroext i1 @test2(%class.PB2* %s_
>> > > ; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28
>> > > ; CHECK-NEXT: rlwinm 4, 4, 0, 28, 28
>> > > ; CHECK-NEXT: sub 3, 4, 3
>> > > +; CHECK-NEXT: not 3, 3
>> > > ; CHECK-NEXT: rldicl 3, 3, 1, 63
>> > > -; CHECK-NEXT: xori 3, 3, 1
>> > > ; CHECK-NEXT: blr
>> > > entry:
>> > > %arrayidx.i6 = bitcast %class.PB2* %s_a to i32*
>> > > @@ -81,8 +81,8 @@ define zeroext i1 @test4(%class.PB2* %s_
>> > > ; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28
>> > > ; CHECK-NEXT: rlwinm 4, 4, 0, 28, 28
>> > > ; CHECK-NEXT: sub 3, 3, 4
>> > > +; CHECK-NEXT: not 3, 3
>> > > ; CHECK-NEXT: rldicl 3, 3, 1, 63
>> > > -; CHECK-NEXT: xori 3, 3, 1
>> > > ; CHECK-NEXT: blr
>> > > entry:
>> > > %arrayidx.i6 = bitcast %class.PB2* %s_a to i32*
>> > >
>> > > Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesigesll.ll
>> > > URL:
>> >
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigesll.ll?rev=347478&r1=347477&r2=347478&view=diff
>> > >
>> >
>> ==============================================================================
>> > > --- llvm/trunk/test/CodeGen/PowerPC/testComparesigesll.ll
>> (original)
>> > > +++ llvm/trunk/test/CodeGen/PowerPC/testComparesigesll.ll Thu Nov
>> > 22 11:24:10 2018
>> > > @@ -39,8 +39,8 @@ entry:
>> > > define signext i32 @test_igesll_z(i64 %a) {
>> > > ; CHECK-LABEL: test_igesll_z:
>> > > ; CHECK: # %bb.0: # %entry
>> > > +; CHECK-NEXT: not r3, r3
>> > > ; CHECK-NEXT: rldicl r3, r3, 1, 63
>> > > -; CHECK-NEXT: xori r3, r3, 1
>> > > ; CHECK-NEXT: blr
>> > > entry:
>> > > %cmp = icmp sgt i64 %a, -1
>> > >
>> > > Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesigeuc.ll
>> > > URL:
>> >
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigeuc.ll?rev=347478&r1=347477&r2=347478&view=diff
>> > >
>> >
>> ==============================================================================
>> > > --- llvm/trunk/test/CodeGen/PowerPC/testComparesigeuc.ll
>> (original)
>> > > +++ llvm/trunk/test/CodeGen/PowerPC/testComparesigeuc.ll Thu Nov
>> > 22 11:24:10 2018
>> > > @@ -15,8 +15,8 @@ entry:
>> > > ret i32 %conv2
>> > > ; CHECK-LABEL: test_igeuc:
>> > > ; CHECK: sub [[REG1:r[0-9]+]], r3, r4
>> > > -; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
>> > > -; CHECK-NEXT: xori r3, [[REG2]], 1
>> > > +; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
>> > > +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
>> > > ; CHECK: blr
>> > > }
>> > >
>> > > @@ -65,8 +65,8 @@ entry:
>> > > ret void
>> > > ; CHECK_LABEL: test_igeuc_store:
>> > > ; CHECK: sub [[REG1:r[0-9]+]], r3, r4
>> > > -; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
>> > > -; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
>> > > +; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
>> > > +; CHECK: rldicl r3, [[REG2]], 1, 63
>> > > ; CHECK: blr
>> > > }
>> > >
>> > >
>> > > Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesigeui.ll
>> > > URL:
>> >
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigeui.ll?rev=347478&r1=347477&r2=347478&view=diff
>> > >
>> >
>> ==============================================================================
>> > > --- llvm/trunk/test/CodeGen/PowerPC/testComparesigeui.ll
>> (original)
>> > > +++ llvm/trunk/test/CodeGen/PowerPC/testComparesigeui.ll Thu Nov
>> > 22 11:24:10 2018
>> > > @@ -15,8 +15,8 @@ entry:
>> > > ret i32 %conv
>> > > ; CHECK-LABEL: test_igeui:
>> > > ; CHECK: sub [[REG1:r[0-9]+]], r3, r4
>> > > -; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
>> > > -; CHECK-NEXT: xori r3, [[REG2]], 1
>> > > +; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
>> > > +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
>> > > ; CHECK: blr
>> > > }
>> > >
>> > > @@ -64,8 +64,8 @@ entry:
>> > > ret void
>> > > ; CHECK_LABEL: test_igeuc_store:
>> > > ; CHECK: sub [[REG1:r[0-9]+]], r3, r4
>> > > -; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
>> > > -; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
>> > > +; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
>> > > +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
>> > > ; CHECK: blr
>> > > }
>> > >
>> > >
>> > > Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesigeus.ll
>> > > URL:
>> >
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigeus.ll?rev=347478&r1=347477&r2=347478&view=diff
>> > >
>> >
>> ==============================================================================
>> > > --- llvm/trunk/test/CodeGen/PowerPC/testComparesigeus.ll
>> (original)
>> > > +++ llvm/trunk/test/CodeGen/PowerPC/testComparesigeus.ll Thu Nov
>> > 22 11:24:10 2018
>> > > @@ -15,8 +15,8 @@ entry:
>> > > ret i32 %conv2
>> > > ; CHECK-LABEL: test_igeus:
>> > > ; CHECK: sub [[REG1:r[0-9]+]], r3, r4
>> > > -; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
>> > > -; CHECK-NEXT: xori r3, [[REG2]], 1
>> > > +; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
>> > > +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
>> > > ; CHECK: blr
>> > > }
>> > >
>> > > @@ -64,8 +64,8 @@ entry:
>> > > ret void
>> > > ; CHECK_LABEL: test_igeus_store:
>> > > ; CHECK: sub [[REG1:r[0-9]+]], r3, r4
>> > > -; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
>> > > -; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
>> > > +; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
>> > > +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
>> > > ; CHECK: blr
>> > > }
>> > >
>> > >
>> > > Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesileuc.ll
>> > > URL:
>> >
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesileuc.ll?rev=347478&r1=347477&r2=347478&view=diff
>> > >
>> >
>> ==============================================================================
>> > > --- llvm/trunk/test/CodeGen/PowerPC/testComparesileuc.ll
>> (original)
>> > > +++ llvm/trunk/test/CodeGen/PowerPC/testComparesileuc.ll Thu Nov
>> > 22 11:24:10 2018
>> > > @@ -15,8 +15,8 @@ entry:
>> > > ret i32 %conv2
>> > > ; CHECK-LABEL: test_ileuc:
>> > > ; CHECK: sub [[REG1:r[0-9]+]], r4, r3
>> > > -; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
>> > > -; CHECK-NEXT: xori r3, [[REG2]], 1
>> > > +; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
>> > > +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
>> > > ; CHECK: blr
>> > > }
>> > >
>> > > @@ -67,8 +67,8 @@ entry:
>> > > ret void
>> > > ; CHECK-LABEL: test_ileuc_store:
>> > > ; CHECK: sub [[REG1:r[0-9]+]], r4, r3
>> > > -; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
>> > > -; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
>> > > +; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
>> > > +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
>> > > ; CHECK: blr
>> > > }
>> > >
>> > >
>> > > Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesileui.ll
>> > > URL:
>> >
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesileui.ll?rev=347478&r1=347477&r2=347478&view=diff
>> > >
>> >
>> ==============================================================================
>> > > --- llvm/trunk/test/CodeGen/PowerPC/testComparesileui.ll
>> (original)
>> > > +++ llvm/trunk/test/CodeGen/PowerPC/testComparesileui.ll Thu Nov
>> > 22 11:24:10 2018
>> > > @@ -15,8 +15,8 @@ entry:
>> > > ret i32 %sub
>> > > ; CHECK-LABEL: test_ileui:
>> > > ; CHECK: sub [[REG1:r[0-9]+]], r4, r3
>> > > -; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
>> > > -; CHECK-NEXT: xori r3, [[REG2]], 1
>> > > +; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
>> > > +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
>> > > ; CHECK: blr
>> > > }
>> > >
>> > > @@ -67,8 +67,8 @@ entry:
>> > > ret void
>> > > ; CHECK-LABEL: test_ileui_store:
>> > > ; CHECK: sub [[REG1:r[0-9]+]], r4, r3
>> > > -; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
>> > > -; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
>> > > +; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
>> > > +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
>> > > ; CHECK: blr
>> > > }
>> > >
>> > >
>> > > Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesileus.ll
>> > > URL:
>> >
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesileus.ll?rev=347478&r1=347477&r2=347478&view=diff
>> > >
>> >
>> ==============================================================================
>> > > --- llvm/trunk/test/CodeGen/PowerPC/testComparesileus.ll
>> (original)
>> > > +++ llvm/trunk/test/CodeGen/PowerPC/testComparesileus.ll Thu Nov
>> > 22 11:24:10 2018
>> > > @@ -15,8 +15,8 @@ entry:
>> > > ret i32 %conv2
>> > > ; CHECK-LABEL: test_ileus:
>> > > ; CHECK: sub [[REG1:r[0-9]+]], r4, r3
>> > > -; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
>> > > -; CHECK-NEXT: xori r3, [[REG2]], 1
>> > > +; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
>> > > +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
>> > > ; CHECK-NEXT: blr
>> > > }
>> > >
>> > > @@ -67,8 +67,8 @@ entry:
>> > > ret void
>> > > ; CHECK-LABEL: test_ileus_store:
>> > > ; CHECK: sub [[REG1:r[0-9]+]], r4, r3
>> > > -; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
>> > > -; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
>> > > +; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
>> > > +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
>> > > ; CHECK: blr
>> > > }
>> > >
>> > >
>> > > Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllgeuc.ll
>> > > URL:
>> >
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgeuc.ll?rev=347478&r1=347477&r2=347478&view=diff
>> > >
>> >
>> ==============================================================================
>> > > --- llvm/trunk/test/CodeGen/PowerPC/testComparesllgeuc.ll
>> (original)
>> > > +++ llvm/trunk/test/CodeGen/PowerPC/testComparesllgeuc.ll Thu Nov
>> > 22 11:24:10 2018
>> > > @@ -15,8 +15,8 @@ entry:
>> > > ret i64 %conv3
>> > > ; CHECK-LABEL: test_llgeuc:
>> > > ; CHECK: sub [[REG1:r[0-9]+]], r3, r4
>> > > -; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
>> > > -; CHECK: xori r3, [[REG2]], 1
>> > > +; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
>> > > +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
>> > > ; CHECK: blr
>> > > }
>> > >
>> > > @@ -64,8 +64,8 @@ entry:
>> > > ret void
>> > > ; CHECK_LABEL: test_llgeuc_store:
>> > > ; CHECK: sub [[REG1:r[0-9]+]], r3, r4
>> > > -; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
>> > > -; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
>> > > +; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
>> > > +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
>> > > ; CHECK: blr
>> > > }
>> > >
>> > >
>> > > Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllgeui.ll
>> > > URL:
>> >
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgeui.ll?rev=347478&r1=347477&r2=347478&view=diff
>> > >
>> >
>> ==============================================================================
>> > > --- llvm/trunk/test/CodeGen/PowerPC/testComparesllgeui.ll
>> (original)
>> > > +++ llvm/trunk/test/CodeGen/PowerPC/testComparesllgeui.ll Thu Nov
>> > 22 11:24:10 2018
>> > > @@ -15,8 +15,8 @@ entry:
>> > > ret i64 %conv1
>> > > ; CHECK-LABEL: test_llgeui:
>> > > ; CHECK: sub [[REG1:r[0-9]+]], r3, r4
>> > > -; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
>> > > -; CHECK-NEXT: xori r3, [[REG2]], 1
>> > > +; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
>> > > +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
>> > > ; CHECK: blr
>> > > }
>> > >
>> > > @@ -64,8 +64,8 @@ entry:
>> > > ret void
>> > > ; CHECK_LABEL: test_igeuc_store:
>> > > ; CHECK: sub [[REG1:r[0-9]+]], r3, r4
>> > > -; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
>> > > -; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
>> > > +; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
>> > > +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
>> > > ; CHECK: blr
>> > > }
>> > >
>> > >
>> > > Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllgeus.ll
>> > > URL:
>> >
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgeus.ll?rev=347478&r1=347477&r2=347478&view=diff
>> > >
>> >
>> ==============================================================================
>> > > --- llvm/trunk/test/CodeGen/PowerPC/testComparesllgeus.ll
>> (original)
>> > > +++ llvm/trunk/test/CodeGen/PowerPC/testComparesllgeus.ll Thu Nov
>> > 22 11:24:10 2018
>> > > @@ -15,8 +15,8 @@ entry:
>> > > ret i64 %conv3
>> > > ; CHECK-LABEL: test_llgeus:
>> > > ; CHECK: sub [[REG1:r[0-9]+]], r3, r4
>> > > -; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
>> > > -; CHECK: xori r3, [[REG2]], 1
>> > > +; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
>> > > +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
>> > > ; CHECK: blr
>> > > }
>> > >
>> > > @@ -64,8 +64,8 @@ entry:
>> > > ret void
>> > > ; CHECK_LABEL: test_llgeus_store:
>> > > ; CHECK: sub [[REG1:r[0-9]+]], r3, r4
>> > > -; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
>> > > -; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
>> > > +; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
>> > > +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
>> > > ; CHECK: blr
>> > > }
>> > >
>> > >
>> > > Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllleuc.ll
>> > > URL:
>> >
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllleuc.ll?rev=347478&r1=347477&r2=347478&view=diff
>> > >
>> >
>> ==============================================================================
>> > > --- llvm/trunk/test/CodeGen/PowerPC/testComparesllleuc.ll
>> (original)
>> > > +++ llvm/trunk/test/CodeGen/PowerPC/testComparesllleuc.ll Thu Nov
>> > 22 11:24:10 2018
>> > > @@ -15,8 +15,8 @@ entry:
>> > > ret i64 %conv3
>> > > ; CHECK-LABEL: test_llleuc:
>> > > ; CHECK: sub [[REG1:r[0-9]+]], r4, r3
>> > > -; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
>> > > -; CHECK-NEXT: xori r3, [[REG2]], 1
>> > > +; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
>> > > +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
>> > > ; CHECK-NEXT: blr
>> > > }
>> > >
>> > > @@ -67,8 +67,8 @@ entry:
>> > > ret void
>> > > ; CHECK-LABEL: test_llleuc_store:
>> > > ; CHECK: sub [[REG1:r[0-9]+]], r4, r3
>> > > -; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
>> > > -; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
>> > > +; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
>> > > +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
>> > > ; CHECK: blr
>> > > }
>> > >
>> > >
>> > > Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllleui.ll
>> > > URL:
>> >
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllleui.ll?rev=347478&r1=347477&r2=347478&view=diff
>> > >
>> >
>> ==============================================================================
>> > > --- llvm/trunk/test/CodeGen/PowerPC/testComparesllleui.ll
>> (original)
>> > > +++ llvm/trunk/test/CodeGen/PowerPC/testComparesllleui.ll Thu Nov
>> > 22 11:24:10 2018
>> > > @@ -15,8 +15,8 @@ entry:
>> > > ret i64 %conv1
>> > > ; CHECK-LABEL: test_llleui:
>> > > ; CHECK: sub [[REG1:r[0-9]+]], r4, r3
>> > > -; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
>> > > -; CHECK-NEXT: xori r3, [[REG2]], 1
>> > > +; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
>> > > +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
>> > > ; CHECK: blr
>> > > }
>> > >
>> > > @@ -67,8 +67,8 @@ entry:
>> > > ret void
>> > > ; CHECK-LABEL: test_llleui_store:
>> > > ; CHECK: sub [[REG1:r[0-9]+]], r4, r3
>> > > -; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
>> > > -; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
>> > > +; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
>> > > +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
>> > > ; CHECK: blr
>> > > }
>> > >
>> > >
>> > > Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllleus.ll
>> > > URL:
>> >
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllleus.ll?rev=347478&r1=347477&r2=347478&view=diff
>> > >
>> >
>> ==============================================================================
>> > > --- llvm/trunk/test/CodeGen/PowerPC/testComparesllleus.ll
>> (original)
>> > > +++ llvm/trunk/test/CodeGen/PowerPC/testComparesllleus.ll Thu Nov
>> > 22 11:24:10 2018
>> > > @@ -15,8 +15,8 @@ entry:
>> > > ret i64 %conv3
>> > > ; CHECK-LABEL: test_llleus:
>> > > ; CHECK: sub [[REG1:r[0-9]+]], r4, r3
>> > > -; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
>> > > -; CHECK-NEXT: xori r3, [[REG2]], 1
>> > > +; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
>> > > +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
>> > > ; CHECK: blr
>> > > }
>> > >
>> > > @@ -67,8 +67,8 @@ entry:
>> > > ret void
>> > > ; CHECK-LABEL: test_llleus_store:
>> > > ; CHECK: sub [[REG1:r[0-9]+]], r4, r3
>> > > -; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
>> > > -; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
>> > > +; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
>> > > +; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
>> > > ; CHECK: blr
>> > > }
>> > >
>> > >
>> > > Modified: llvm/trunk/test/CodeGen/X86/not-and-simplify.ll
>> > > URL:
>> >
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/not-and-simplify.ll?rev=347478&r1=347477&r2=347478&view=diff
>> > >
>> >
>> ==============================================================================
>> > > --- llvm/trunk/test/CodeGen/X86/not-and-simplify.ll (original)
>> > > +++ llvm/trunk/test/CodeGen/X86/not-and-simplify.ll Thu Nov 22
>> > 11:24:10 2018
>> > > @@ -8,8 +8,8 @@ define i32 @shrink_xor_constant1(i32 %x)
>> > > ; ALL-LABEL: shrink_xor_constant1:
>> > > ; ALL: # %bb.0:
>> > > ; ALL-NEXT: movl %edi, %eax
>> > > +; ALL-NEXT: notl %eax
>> > > ; ALL-NEXT: shrl $31, %eax
>> > > -; ALL-NEXT: xorl $1, %eax
>> > > ; ALL-NEXT: retq
>> > > %sh = lshr i32 %x, 31
>> > > %not = xor i32 %sh, -1
>> > > @@ -35,8 +35,8 @@ define i8 @shrink_xor_constant2(i8 %x) {
>> > > ; ALL-LABEL: shrink_xor_constant2:
>> > > ; ALL: # %bb.0:
>> > > ; ALL-NEXT: movl %edi, %eax
>> > > +; ALL-NEXT: notb %al
>> > > ; ALL-NEXT: shlb $5, %al
>> > > -; ALL-NEXT: xorb $-32, %al
>> > > ; ALL-NEXT: # kill: def $al killed $al killed $eax
>> > > ; ALL-NEXT: retq
>> > > %sh = shl i8 %x, 5
>> > >
>> > > Modified: llvm/trunk/test/CodeGen/X86/xor.ll
>> > > URL:
>> >
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/xor.ll?rev=347478&r1=347477&r2=347478&view=diff
>> > >
>> >
>> ==============================================================================
>> > > --- llvm/trunk/test/CodeGen/X86/xor.ll (original)
>> > > +++ llvm/trunk/test/CodeGen/X86/xor.ll Thu Nov 22 11:24:10 2018
>> > > @@ -493,18 +493,18 @@ define %struct.ref_s* @test12(%struct.re
>> > <http://struct.re>
>> > > ;
>> > > ; X64-LIN-LABEL: test12:
>> > > ; X64-LIN: # %bb.0:
>> > > -; X64-LIN-NEXT: xorq $-1, %rdx
>> > > -; X64-LIN-NEXT: shlq $32, %rdx
>> > > -; X64-LIN-NEXT: sarq $28, %rdx
>> > > -; X64-LIN-NEXT: leaq (%rdx,%rdi), %rax
>> > > +; X64-LIN-NEXT: notl %edx
>> > > +; X64-LIN-NEXT: movslq %edx, %rax
>> > > +; X64-LIN-NEXT: shlq $4, %rax
>> > > +; X64-LIN-NEXT: addq %rdi, %rax
>> > > ; X64-LIN-NEXT: retq
>> > > ;
>> > > ; X64-WIN-LABEL: test12:
>> > > ; X64-WIN: # %bb.0:
>> > > -; X64-WIN-NEXT: xorq $-1, %r8
>> > > -; X64-WIN-NEXT: shlq $32, %r8
>> > > -; X64-WIN-NEXT: sarq $28, %r8
>> > > -; X64-WIN-NEXT: leaq (%r8,%rcx), %rax
>> > > +; X64-WIN-NEXT: notl %r8d
>> > > +; X64-WIN-NEXT: movslq %r8d, %rax
>> > > +; X64-WIN-NEXT: shlq $4, %rax
>> > > +; X64-WIN-NEXT: addq %rcx, %rax
>> > > ; X64-WIN-NEXT: retq
>> > > %neg = shl i64 %intval, 32
>> > > %sext = xor i64 %neg, -4294967296
>> > > @@ -518,23 +518,20 @@ define i32 @PR39657(i8* %p, i64 %x) {
>> > > ; X32: # %bb.0:
>> > > ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
>> > > ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
>> > > -; X32-NEXT: shll $2, %ecx
>> > > -; X32-NEXT: xorl $-4, %ecx
>> > > -; X32-NEXT: movl (%eax,%ecx), %eax
>> > > +; X32-NEXT: notl %ecx
>> > > +; X32-NEXT: movl (%eax,%ecx,4), %eax
>> > > ; X32-NEXT: retl
>> > > ;
>> > > ; X64-LIN-LABEL: PR39657:
>> > > ; X64-LIN: # %bb.0:
>> > > -; X64-LIN-NEXT: shlq $2, %rsi
>> > > -; X64-LIN-NEXT: xorq $-4, %rsi
>> > > -; X64-LIN-NEXT: movl (%rdi,%rsi), %eax
>> > > +; X64-LIN-NEXT: notq %rsi
>> > > +; X64-LIN-NEXT: movl (%rdi,%rsi,4), %eax
>> > > ; X64-LIN-NEXT: retq
>> > > ;
>> > > ; X64-WIN-LABEL: PR39657:
>> > > ; X64-WIN: # %bb.0:
>> > > -; X64-WIN-NEXT: shlq $2, %rdx
>> > > -; X64-WIN-NEXT: xorq $-4, %rdx
>> > > -; X64-WIN-NEXT: movl (%rcx,%rdx), %eax
>> > > +; X64-WIN-NEXT: notq %rdx
>> > > +; X64-WIN-NEXT: movl (%rcx,%rdx,4), %eax
>> > > ; X64-WIN-NEXT: retq
>> > > %sh = shl i64 %x, 2
>> > > %mul = xor i64 %sh, -4
>> > >
>> > >
>> > > _______________________________________________
>> > > llvm-commits mailing list
>> > > llvm-commits at lists.llvm.org <mailto:llvm-commits at lists.llvm.org>
>> > > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits
>> > >
>> >
>>
>>
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