[llvm] r347494 - [ARM][AsmParser] Improve debug printing of parsed asm operands
Oliver Stannard via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 23 06:27:22 PST 2018
Author: olista01
Date: Fri Nov 23 06:27:21 2018
New Revision: 347494
URL: http://llvm.org/viewvc/llvm-project?rev=347494&view=rev
Log:
[ARM][AsmParser] Improve debug printing of parsed asm operands
In ARMOperand::print:
- Print human-readable register names, instead of numbers.
- Print the correct names for IT condition masks (these were in the wrong order
before).
- Print all parts of memory operands, not just the base register.
This makes the output of llvm-mc -show-inst-operands more readable.
Differential revision: https://reviews.llvm.org/D54850
Modified:
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=347494&r1=347493&r2=347494&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Nov 23 06:27:21 2018
@@ -8,6 +8,7 @@
//===----------------------------------------------------------------------===//
#include "ARMFeatures.h"
+#include "InstPrinter/ARMInstPrinter.h"
#include "Utils/ARMBaseInfo.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "MCTargetDesc/ARMBaseInfo.h"
@@ -3205,17 +3206,26 @@ public:
} // end anonymous namespace.
void ARMOperand::print(raw_ostream &OS) const {
+ auto RegName = [](unsigned Reg) {
+ if (Reg)
+ return ARMInstPrinter::getRegisterName(Reg);
+ else
+ return "noreg";
+ };
+
switch (Kind) {
case k_CondCode:
OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
break;
case k_CCOut:
- OS << "<ccout " << getReg() << ">";
+ OS << "<ccout " << RegName(getReg()) << ">";
break;
case k_ITCondMask: {
static const char *const MaskStr[] = {
- "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
- "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
+ "(invalid)", "(teee)", "(tee)", "(teet)",
+ "(te)", "(tete)", "(tet)", "(tett)",
+ "(t)", "(ttee)", "(tte)", "(ttet)",
+ "(tt)", "(ttte)", "(ttt)", "(tttt)"
};
assert((ITMask.Mask & 0xf) == ITMask.Mask);
OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
@@ -3249,13 +3259,25 @@ void ARMOperand::print(raw_ostream &OS)
OS << "<ARM_TSB::" << TraceSyncBOptToString(getTraceSyncBarrierOpt()) << ">";
break;
case k_Memory:
- OS << "<memory "
- << " base:" << Memory.BaseRegNum;
+ OS << "<memory";
+ if (Memory.BaseRegNum)
+ OS << " base:" << RegName(Memory.BaseRegNum);
+ if (Memory.OffsetImm)
+ OS << " offset-imm:" << *Memory.OffsetImm;
+ if (Memory.OffsetRegNum)
+ OS << " offset-reg:" << (Memory.isNegative ? "-" : "")
+ << RegName(Memory.OffsetRegNum);
+ if (Memory.ShiftType != ARM_AM::no_shift) {
+ OS << " shift-type:" << ARM_AM::getShiftOpcStr(Memory.ShiftType);
+ OS << " shift-imm:" << Memory.ShiftImm;
+ }
+ if (Memory.Alignment)
+ OS << " alignment:" << Memory.Alignment;
OS << ">";
break;
case k_PostIndexRegister:
OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
- << PostIdxReg.RegNum;
+ << RegName(PostIdxReg.RegNum);
if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
<< PostIdxReg.ShiftImm;
@@ -3271,23 +3293,21 @@ void ARMOperand::print(raw_ostream &OS)
break;
}
case k_Register:
- OS << "<register " << getReg() << ">";
+ OS << "<register " << RegName(getReg()) << ">";
break;
case k_ShifterImmediate:
OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
<< " #" << ShifterImm.Imm << ">";
break;
case k_ShiftedRegister:
- OS << "<so_reg_reg "
- << RegShiftedReg.SrcReg << " "
- << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
- << " " << RegShiftedReg.ShiftReg << ">";
+ OS << "<so_reg_reg " << RegName(RegShiftedReg.SrcReg) << " "
+ << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) << " "
+ << RegName(RegShiftedReg.ShiftReg) << ">";
break;
case k_ShiftedImmediate:
- OS << "<so_reg_imm "
- << RegShiftedImm.SrcReg << " "
- << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
- << " #" << RegShiftedImm.ShiftImm << ">";
+ OS << "<so_reg_imm " << RegName(RegShiftedImm.SrcReg) << " "
+ << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) << " #"
+ << RegShiftedImm.ShiftImm << ">";
break;
case k_RotateImmediate:
OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
@@ -3311,7 +3331,7 @@ void ARMOperand::print(raw_ostream &OS)
const SmallVectorImpl<unsigned> &RegList = getRegList();
for (SmallVectorImpl<unsigned>::const_iterator
I = RegList.begin(), E = RegList.end(); I != E; ) {
- OS << *I;
+ OS << RegName(*I);
if (++I < E) OS << ", ";
}
@@ -3320,15 +3340,15 @@ void ARMOperand::print(raw_ostream &OS)
}
case k_VectorList:
OS << "<vector_list " << VectorList.Count << " * "
- << VectorList.RegNum << ">";
+ << RegName(VectorList.RegNum) << ">";
break;
case k_VectorListAllLanes:
OS << "<vector_list(all lanes) " << VectorList.Count << " * "
- << VectorList.RegNum << ">";
+ << RegName(VectorList.RegNum) << ">";
break;
case k_VectorListIndexed:
OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
- << VectorList.Count << " * " << VectorList.RegNum << ">";
+ << VectorList.Count << " * " << RegName(VectorList.RegNum) << ">";
break;
case k_Token:
OS << "'" << getToken() << "'";
More information about the llvm-commits
mailing list