[PATCH] D54846: [CodeGen][NFC] Make `TII::getMemOpBaseImmOfs` return a base operand

[Francis Visoiu Mistrih via Phabricator via llvm-commits]

thegameg created this revision.
thegameg added reviewers: sdesmalen, paquette, eli.friedman, niravd, qcolombet, arsenm, kparzysz, jpienaar, RKSimon, craig.topper, MatzeB, dsanders.
Herald added subscribers: javed.absar, nhaehnle, wdng, jvesely.

Currently, instructions doing memory accesses through a base operand that is not a register can not be analyzed using `TII::getMemOpBaseRegImmOfs`.

This means that functions such as `TII::shouldClusterMemOps` will bail out on instructions using an FI as a base instead of a register.

The goal of this patch is to refactor all this to return a base operand instead of a base register.

Then in a separate patch, I will add FI support to the mem op clustering in the MachineScheduler.


https://reviews.llvm.org/D54846

Files:
  include/llvm/CodeGen/TargetInstrInfo.h
  lib/CodeGen/ImplicitNullChecks.cpp
  lib/CodeGen/MachinePipeliner.cpp
  lib/CodeGen/MachineScheduler.cpp
  lib/CodeGen/MachineSink.cpp
  lib/Target/AArch64/AArch64InstrInfo.cpp
  lib/Target/AArch64/AArch64InstrInfo.h
  lib/Target/AArch64/AArch64StorePairSuppress.cpp
  lib/Target/AMDGPU/SIInstrInfo.cpp
  lib/Target/AMDGPU/SIInstrInfo.h
  lib/Target/AMDGPU/SIMachineScheduler.cpp
  lib/Target/Hexagon/HexagonInstrInfo.cpp
  lib/Target/Hexagon/HexagonInstrInfo.h
  lib/Target/Hexagon/HexagonSubtarget.cpp
  lib/Target/Lanai/LanaiInstrInfo.cpp
  lib/Target/Lanai/LanaiInstrInfo.h
  lib/Target/X86/X86InstrInfo.cpp
  lib/Target/X86/X86InstrInfo.h

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