[llvm] r347482 - [LegalizeVectorTypes] Don't use SplitVecOp_TruncateHelper if we're heading towards scalarizing the type.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 22 18:32:13 PST 2018
Author: ctopper
Date: Thu Nov 22 18:32:13 2018
New Revision: 347482
URL: http://llvm.org/viewvc/llvm-project?rev=347482&view=rev
Log:
[LegalizeVectorTypes] Don't use SplitVecOp_TruncateHelper if we're heading towards scalarizing the type.
This code takes a truncate, fp_to_int, or int_to_fp with a legal result type and an input type that needs to be split and enlarges the elements in the result type before doing the split. Then inserts a follow up truncate or fp_round after concatenating the two halves back together.
But if the input type of the original op is being split on its way to ultimately being scalarized we're just going to end up building a vector from scalars and then truncating or rounding it in the vector register. Seems kind of silly to enlarge the result element type of the operation only to end up with scalar code and then building a vector with large elements only to make the elements smaller again in the vector register. Seems better to just try to get away producing smaller result types in the scalarized code.
The X86 test case that changes is a pretty contrived test case that exists because of a bug we used to have in our AVG matching code. I think the code is better now, but its not realistic anyway.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
llvm/trunk/test/CodeGen/ARM/vector-DAGCombine.ll
llvm/trunk/test/CodeGen/NVPTX/f16x2-instructions.ll
llvm/trunk/test/CodeGen/X86/avg.ll
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=347482&r1=347481&r2=347482&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Thu Nov 22 18:32:13 2018
@@ -2260,9 +2260,18 @@ SDValue DAGTypeLegalizer::SplitVecOp_Tru
return SplitVecOp_UnaryOp(N);
SDLoc DL(N);
+ // Don't touch if this will be scalarized.
+ EVT FinalVT = InVT;
+ while (getTypeAction(FinalVT) == TargetLowering::TypeSplitVector)
+ FinalVT = FinalVT.getHalfNumVectorElementsVT(*DAG.getContext());
+
+ if (getTypeAction(FinalVT) == TargetLowering::TypeScalarizeVector)
+ return SplitVecOp_UnaryOp(N);
+
// Get the split input vector.
SDValue InLoVec, InHiVec;
GetSplitVector(InVec, InLoVec, InHiVec);
+
// Truncate them to 1/2 the element size.
EVT HalfElementVT = IsFloat ?
EVT::getFloatingPointVT(InElementSize/2) :
Modified: llvm/trunk/test/CodeGen/ARM/vector-DAGCombine.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vector-DAGCombine.ll?rev=347482&r1=347481&r2=347482&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vector-DAGCombine.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vector-DAGCombine.ll Thu Nov 22 18:32:13 2018
@@ -237,17 +237,10 @@ entry:
; illegal type to a legal type.
define <2 x i8> @test_truncate(<2 x i128> %in) {
; CHECK-LABEL: test_truncate:
-; REG2 Should map on the same Q register as REG1, i.e., REG2 = REG1 - 1, but we
-; cannot express that.
-; CHECK: vmov.32 [[REG2:d[0-9]+]][0], r0
+; CHECK: vmov.32 [[REG:d[0-9]+]][0], r0
; CHECK-NEXT: mov [[BASE:r[0-9]+]], sp
-; CHECK-NEXT: vld1.32 {[[REG1:d[0-9]+]][0]}, {{\[}}[[BASE]]:32]
-; CHECK-NEXT: add [[BASE2:r[0-9]+]], [[BASE]], #4
-; CHECK-NEXT: vmov.32 [[REG2]][1], r1
-; CHECK-NEXT: vld1.32 {[[REG1]][1]}, {{\[}}[[BASE2]]:32]
-; The Q register used here should match floor(REG1/2), but we cannot express that.
-; CHECK-NEXT: vmovn.i64 [[RES:d[0-9]+]], q{{[0-9]+}}
-; CHECK-NEXT: vmov r0, r1, [[RES]]
+; CHECK-NEXT: vld1.32 {[[REG]][1]}, {{\[}}[[BASE]]:32]
+; CHECK-NEXT: vmov r0, r1, [[REG]]
entry:
%res = trunc <2 x i128> %in to <2 x i8>
ret <2 x i8> %res
Modified: llvm/trunk/test/CodeGen/NVPTX/f16x2-instructions.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/f16x2-instructions.ll?rev=347482&r1=347481&r2=347482&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/NVPTX/f16x2-instructions.ll (original)
+++ llvm/trunk/test/CodeGen/NVPTX/f16x2-instructions.ll Thu Nov 22 18:32:13 2018
@@ -823,10 +823,8 @@ define <2 x half> @test_uitofp_2xi32(<2
; CHECK-LABEL: test_uitofp_2xi64(
; CHECK: ld.param.v2.u64 {[[A0:%rd[0-9]+]], [[A1:%rd[0-9]+]]}, [test_uitofp_2xi64_param_0];
-; CHECK-DAG: cvt.rn.f32.u64 [[F0:%f[0-9]+]], [[A0]];
-; CHECK-DAG: cvt.rn.f32.u64 [[F1:%f[0-9]+]], [[A1]];
-; CHECK-DAG: cvt.rn.f16.f32 [[R0:%h[0-9]+]], [[F0]];
-; CHECK-DAG: cvt.rn.f16.f32 [[R1:%h[0-9]+]], [[F1]];
+; CHECK-DAG: cvt.rn.f16.u64 [[R0:%h[0-9]+]], [[A0]];
+; CHECK-DAG: cvt.rn.f16.u64 [[R1:%h[0-9]+]], [[A1]];
; CHECK: mov.b32 [[R:%hh[0-9]+]], {[[R0]], [[R1]]}
; CHECK: st.param.b32 [func_retval0+0], [[R]];
; CHECK: ret;
@@ -849,10 +847,8 @@ define <2 x half> @test_sitofp_2xi32(<2
; CHECK-LABEL: test_sitofp_2xi64(
; CHECK: ld.param.v2.u64 {[[A0:%rd[0-9]+]], [[A1:%rd[0-9]+]]}, [test_sitofp_2xi64_param_0];
-; CHECK-DAG: cvt.rn.f32.s64 [[F0:%f[0-9]+]], [[A0]];
-; CHECK-DAG: cvt.rn.f32.s64 [[F1:%f[0-9]+]], [[A1]];
-; CHECK-DAG: cvt.rn.f16.f32 [[R0:%h[0-9]+]], [[F0]];
-; CHECK-DAG: cvt.rn.f16.f32 [[R1:%h[0-9]+]], [[F1]];
+; CHECK-DAG: cvt.rn.f16.s64 [[R0:%h[0-9]+]], [[A0]];
+; CHECK-DAG: cvt.rn.f16.s64 [[R1:%h[0-9]+]], [[A1]];
; CHECK: mov.b32 [[R:%hh[0-9]+]], {[[R0]], [[R1]]}
; CHECK: st.param.b32 [func_retval0+0], [[R]];
; CHECK: ret;
Modified: llvm/trunk/test/CodeGen/X86/avg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avg.ll?rev=347482&r1=347481&r2=347482&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avg.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avg.ll Thu Nov 22 18:32:13 2018
@@ -1918,13 +1918,12 @@ define void @not_avg_v16i8_wide_constant
; SSE2-NEXT: pushq %r13
; SSE2-NEXT: pushq %r12
; SSE2-NEXT: pushq %rbx
-; SSE2-NEXT: movaps (%rdi), %xmm1
-; SSE2-NEXT: movaps (%rsi), %xmm0
-; SSE2-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp)
-; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
-; SSE2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; SSE2-NEXT: movaps (%rdi), %xmm0
+; SSE2-NEXT: movaps (%rsi), %xmm1
+; SSE2-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %r13d
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
@@ -1932,34 +1931,37 @@ define void @not_avg_v16i8_wide_constant
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %r14d
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %r15d
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %r12d
-; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %r13d
-; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %r10d
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %r11d
+; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %r10d
+; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %r9d
+; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
+; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %edi
+; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ebp
+; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ebx
+; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
+; SSE2-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %esi
-; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
+; SSE2-NEXT: leal -1(%rdx,%rsi), %edx
+; SSE2-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
-; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ebp
+; SSE2-NEXT: leal -1(%rbx,%rdx), %edx
+; SSE2-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
+; SSE2-NEXT: leal -1(%rbp,%rdx), %edx
+; SSE2-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
+; SSE2-NEXT: leal -1(%rdi,%rdx), %r8d
+; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
+; SSE2-NEXT: leal -1(%rax,%rdx), %edi
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
-; SSE2-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
-; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %r9d
-; SSE2-NEXT: leaq -1(%rax,%r9), %rax
-; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ebx
-; SSE2-NEXT: leaq -1(%rbp,%rbx), %rbp
-; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ebx
-; SSE2-NEXT: leaq -1(%rdx,%rbx), %rdx
-; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ebx
-; SSE2-NEXT: leaq -1(%rcx,%rbx), %rcx
-; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ebx
-; SSE2-NEXT: leaq -1(%rsi,%rbx), %rsi
-; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ebx
-; SSE2-NEXT: leaq -1(%rdi,%rbx), %r8
-; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ebx
-; SSE2-NEXT: leaq -1(%r11,%rbx), %r9
-; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ebx
-; SSE2-NEXT: leaq -1(%r10,%rbx), %r11
-; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ebx
-; SSE2-NEXT: leaq -1(%r13,%rbx), %r13
+; SSE2-NEXT: leal -1(%rcx,%rax), %edx
+; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
+; SSE2-NEXT: leal -1(%r9,%rax), %ecx
+; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %esi
+; SSE2-NEXT: leal -1(%r10,%rsi), %eax
+; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %esi
+; SSE2-NEXT: leaq -1(%r11,%rsi), %rsi
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ebx
; SSE2-NEXT: leaq -1(%r12,%rbx), %r12
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ebx
@@ -1967,71 +1969,67 @@ define void @not_avg_v16i8_wide_constant
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ebx
; SSE2-NEXT: leaq -1(%r14,%rbx), %r14
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ebx
-; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdi # 8-byte Reload
-; SSE2-NEXT: leaq -1(%rdi,%rbx), %rdi
-; SSE2-NEXT: movq %rdi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rbp # 8-byte Reload
+; SSE2-NEXT: leaq -1(%rbp,%rbx), %r11
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ebx
-; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdi # 8-byte Reload
-; SSE2-NEXT: leaq -1(%rdi,%rbx), %rbx
-; SSE2-NEXT: movq %rbx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rbp # 8-byte Reload
+; SSE2-NEXT: leaq -1(%rbp,%rbx), %r10
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ebx
-; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdi # 8-byte Reload
-; SSE2-NEXT: leaq -1(%rdi,%rbx), %rbx
-; SSE2-NEXT: movq %rbx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; SSE2-NEXT: leaq -1(%r13,%rbx), %r9
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ebx
-; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r10 # 8-byte Reload
-; SSE2-NEXT: leaq -1(%r10,%rbx), %rbx
-; SSE2-NEXT: shrq %rax
+; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r13 # 8-byte Reload
+; SSE2-NEXT: leaq -1(%r13,%rbx), %rbx
+; SSE2-NEXT: shrl %eax
; SSE2-NEXT: movd %eax, %xmm8
-; SSE2-NEXT: shrq %rbp
-; SSE2-NEXT: movd %ebp, %xmm15
-; SSE2-NEXT: shrq %rdx
+; SSE2-NEXT: shrl %ecx
+; SSE2-NEXT: movd %ecx, %xmm15
+; SSE2-NEXT: shrl %edx
; SSE2-NEXT: movd %edx, %xmm9
-; SSE2-NEXT: shrq %rcx
-; SSE2-NEXT: movd %ecx, %xmm2
+; SSE2-NEXT: shrl %edi
+; SSE2-NEXT: movd %edi, %xmm2
+; SSE2-NEXT: shrl %r8d
+; SSE2-NEXT: movd %r8d, %xmm10
+; SSE2-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
+; SSE2-NEXT: shrl %eax
+; SSE2-NEXT: movd %eax, %xmm6
+; SSE2-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
+; SSE2-NEXT: shrl %eax
+; SSE2-NEXT: movd %eax, %xmm11
+; SSE2-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
+; SSE2-NEXT: shrl %eax
+; SSE2-NEXT: movd %eax, %xmm4
; SSE2-NEXT: shrq %rsi
-; SSE2-NEXT: movd %esi, %xmm10
-; SSE2-NEXT: shrq %r8
-; SSE2-NEXT: movd %r8d, %xmm6
-; SSE2-NEXT: shrq %r9
-; SSE2-NEXT: movd %r9d, %xmm11
-; SSE2-NEXT: shrq %r11
-; SSE2-NEXT: movd %r11d, %xmm5
-; SSE2-NEXT: shrq %r13
-; SSE2-NEXT: movd %r13d, %xmm12
+; SSE2-NEXT: movd %esi, %xmm12
; SSE2-NEXT: shrq %r12
; SSE2-NEXT: movd %r12d, %xmm3
; SSE2-NEXT: shrq %r15
; SSE2-NEXT: movd %r15d, %xmm13
; SSE2-NEXT: shrq %r14
; SSE2-NEXT: movd %r14d, %xmm7
-; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
-; SSE2-NEXT: shrq %rax
-; SSE2-NEXT: movd %eax, %xmm14
-; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
-; SSE2-NEXT: shrq %rax
-; SSE2-NEXT: movd %eax, %xmm4
-; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
-; SSE2-NEXT: shrq %rax
-; SSE2-NEXT: movd %eax, %xmm0
+; SSE2-NEXT: shrq %r11
+; SSE2-NEXT: movd %r11d, %xmm14
+; SSE2-NEXT: shrq %r10
+; SSE2-NEXT: movd %r10d, %xmm5
+; SSE2-NEXT: shrq %r9
+; SSE2-NEXT: movd %r9d, %xmm0
; SSE2-NEXT: shrq %rbx
; SSE2-NEXT: movd %ebx, %xmm1
; SSE2-NEXT: punpcklbw {{.*#+}} xmm15 = xmm15[0],xmm8[0],xmm15[1],xmm8[1],xmm15[2],xmm8[2],xmm15[3],xmm8[3],xmm15[4],xmm8[4],xmm15[5],xmm8[5],xmm15[6],xmm8[6],xmm15[7],xmm8[7]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm9[0],xmm2[1],xmm9[1],xmm2[2],xmm9[2],xmm2[3],xmm9[3],xmm2[4],xmm9[4],xmm2[5],xmm9[5],xmm2[6],xmm9[6],xmm2[7],xmm9[7]
; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm15[0],xmm2[1],xmm15[1],xmm2[2],xmm15[2],xmm2[3],xmm15[3]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm10[0],xmm6[1],xmm10[1],xmm6[2],xmm10[2],xmm6[3],xmm10[3],xmm6[4],xmm10[4],xmm6[5],xmm10[5],xmm6[6],xmm10[6],xmm6[7],xmm10[7]
-; SSE2-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm11[0],xmm5[1],xmm11[1],xmm5[2],xmm11[2],xmm5[3],xmm11[3],xmm5[4],xmm11[4],xmm5[5],xmm11[5],xmm5[6],xmm11[6],xmm5[7],xmm11[7]
-; SSE2-NEXT: punpcklwd {{.*#+}} xmm5 = xmm5[0],xmm6[0],xmm5[1],xmm6[1],xmm5[2],xmm6[2],xmm5[3],xmm6[3]
-; SSE2-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1]
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm11[0],xmm4[1],xmm11[1],xmm4[2],xmm11[2],xmm4[3],xmm11[3],xmm4[4],xmm11[4],xmm4[5],xmm11[5],xmm4[6],xmm11[6],xmm4[7],xmm11[7]
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm6[0],xmm4[1],xmm6[1],xmm4[2],xmm6[2],xmm4[3],xmm6[3]
+; SSE2-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm12[0],xmm3[1],xmm12[1],xmm3[2],xmm12[2],xmm3[3],xmm12[3],xmm3[4],xmm12[4],xmm3[5],xmm12[5],xmm3[6],xmm12[6],xmm3[7],xmm12[7]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm7 = xmm7[0],xmm13[0],xmm7[1],xmm13[1],xmm7[2],xmm13[2],xmm7[3],xmm13[3],xmm7[4],xmm13[4],xmm7[5],xmm13[5],xmm7[6],xmm13[6],xmm7[7],xmm13[7]
; SSE2-NEXT: punpcklwd {{.*#+}} xmm7 = xmm7[0],xmm3[0],xmm7[1],xmm3[1],xmm7[2],xmm3[2],xmm7[3],xmm3[3]
-; SSE2-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm14[0],xmm4[1],xmm14[1],xmm4[2],xmm14[2],xmm4[3],xmm14[3],xmm4[4],xmm14[4],xmm4[5],xmm14[5],xmm4[6],xmm14[6],xmm4[7],xmm14[7]
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm14[0],xmm5[1],xmm14[1],xmm5[2],xmm14[2],xmm5[3],xmm14[3],xmm5[4],xmm14[4],xmm5[5],xmm14[5],xmm5[6],xmm14[6],xmm5[7],xmm14[7]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
-; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3]
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm5[0],xmm1[1],xmm5[1],xmm1[2],xmm5[2],xmm1[3],xmm5[3]
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm7[0],xmm1[1],xmm7[1]
-; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm5[0]
-; SSE2-NEXT: movdqu %xmm1, (%rax)
+; SSE2-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm1[0]
+; SSE2-NEXT: movdqu %xmm4, (%rax)
; SSE2-NEXT: popq %rbx
; SSE2-NEXT: popq %r12
; SSE2-NEXT: popq %r13
@@ -2048,236 +2046,115 @@ define void @not_avg_v16i8_wide_constant
; AVX1-NEXT: pushq %r13
; AVX1-NEXT: pushq %r12
; AVX1-NEXT: pushq %rbx
-; AVX1-NEXT: subq $24, %rsp
-; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm2 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
-; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm4 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
+; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
+; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm4 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm3 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
-; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm5 = xmm4[4],xmm1[4],xmm4[5],xmm1[5],xmm4[6],xmm1[6],xmm4[7],xmm1[7]
-; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm6 = xmm5[2],xmm1[2],xmm5[3],xmm1[3]
-; AVX1-NEXT: vpextrq $1, %xmm6, %rdi
-; AVX1-NEXT: vmovq %xmm6, %rbp
-; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm5 = xmm5[0],zero,xmm5[1],zero
-; AVX1-NEXT: vpextrq $1, %xmm5, %rbx
-; AVX1-NEXT: vmovq %xmm5, %rsi
-; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm4 = xmm4[0],zero,xmm4[1],zero,xmm4[2],zero,xmm4[3],zero
-; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm5 = xmm4[2],xmm1[2],xmm4[3],xmm1[3]
-; AVX1-NEXT: vpextrq $1, %xmm5, %rdx
-; AVX1-NEXT: vmovq %xmm5, %rcx
-; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm5 = xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7]
-; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm6 = xmm5[2],xmm1[2],xmm5[3],xmm1[3]
-; AVX1-NEXT: vpextrq $1, %xmm6, %r13
-; AVX1-NEXT: vmovq %xmm6, %r12
-; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm5 = xmm5[0],zero,xmm5[1],zero
-; AVX1-NEXT: vpextrq $1, %xmm5, %r11
-; AVX1-NEXT: vmovq %xmm5, %r14
-; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero
-; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm5 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
-; AVX1-NEXT: vpextrq $1, %xmm5, %r9
-; AVX1-NEXT: vmovq %xmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill
-; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm4 = xmm4[0],zero,xmm4[1],zero
-; AVX1-NEXT: vpextrq $1, %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill
-; AVX1-NEXT: vmovq %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill
+; AVX1-NEXT: vpxor %xmm7, %xmm7, %xmm7
+; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm6 = xmm1[4],xmm7[4],xmm1[5],xmm7[5],xmm1[6],xmm7[6],xmm1[7],xmm7[7]
+; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm0[4],xmm7[4],xmm0[5],xmm7[5],xmm0[6],xmm7[6],xmm0[7],xmm7[7]
+; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm5 = xmm2[2],xmm7[2],xmm2[3],xmm7[3]
+; AVX1-NEXT: vpextrq $1, %xmm5, %r15
+; AVX1-NEXT: vmovq %xmm5, %r12
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm2 = xmm2[0],zero,xmm2[1],zero
-; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm3[4],xmm1[4],xmm3[5],xmm1[5],xmm3[6],xmm1[6],xmm3[7],xmm1[7]
-; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm5 = xmm4[2],xmm1[2],xmm4[3],xmm1[3]
-; AVX1-NEXT: vpextrq $1, %xmm5, %rax
-; AVX1-NEXT: addq %rdi, %rax
-; AVX1-NEXT: movq %rax, %rdi
-; AVX1-NEXT: vmovq %xmm5, %rax
-; AVX1-NEXT: addq %rbp, %rax
-; AVX1-NEXT: movq %rax, %rbp
-; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm4 = xmm4[0],zero,xmm4[1],zero
-; AVX1-NEXT: vpextrq $1, %xmm4, %r15
-; AVX1-NEXT: addq %rbx, %r15
-; AVX1-NEXT: vmovq %xmm4, %r10
-; AVX1-NEXT: addq %rsi, %r10
-; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm3 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero
-; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm4 = xmm3[2],xmm1[2],xmm3[3],xmm1[3]
-; AVX1-NEXT: vpextrq $1, %xmm4, %rax
-; AVX1-NEXT: addq %rdx, %rax
-; AVX1-NEXT: movq %rax, %rdx
-; AVX1-NEXT: vmovq %xmm4, %r8
-; AVX1-NEXT: addq %rcx, %r8
-; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
-; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm5 = xmm4[2],xmm1[2],xmm4[3],xmm1[3]
-; AVX1-NEXT: vpextrq $1, %xmm5, %rcx
-; AVX1-NEXT: addq %r13, %rcx
-; AVX1-NEXT: vmovq %xmm5, %rax
-; AVX1-NEXT: addq %r12, %rax
-; AVX1-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm4 = xmm4[0],zero,xmm4[1],zero
-; AVX1-NEXT: vpextrq $1, %xmm4, %rax
-; AVX1-NEXT: addq %r11, %rax
-; AVX1-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX1-NEXT: vmovq %xmm4, %rax
-; AVX1-NEXT: addq %r14, %rax
-; AVX1-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; AVX1-NEXT: vpextrq $1, %xmm2, %r11
+; AVX1-NEXT: vmovq %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill
; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
-; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm1 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; AVX1-NEXT: vpextrq $1, %xmm1, %rax
-; AVX1-NEXT: addq %r9, %rax
-; AVX1-NEXT: movq %rax, %r13
-; AVX1-NEXT: vmovq %xmm1, %rbx
-; AVX1-NEXT: addq {{[-0-9]+}}(%r{{[sb]}}p), %rbx # 8-byte Folded Reload
-; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm3[0],zero,xmm3[1],zero
-; AVX1-NEXT: vpextrq $1, %xmm1, %rax
-; AVX1-NEXT: addq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Folded Reload
-; AVX1-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX1-NEXT: vmovq %xmm1, %rax
-; AVX1-NEXT: addq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Folded Reload
-; AVX1-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX1-NEXT: vpextrq $1, %xmm2, %rax
+; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm2 = xmm0[2],xmm7[2],xmm0[3],xmm7[3]
+; AVX1-NEXT: vpextrq $1, %xmm2, %r13
+; AVX1-NEXT: vmovq %xmm2, %r14
+; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm2 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
-; AVX1-NEXT: vpextrq $1, %xmm0, %rsi
-; AVX1-NEXT: addq %rax, %rsi
-; AVX1-NEXT: movq %rsi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX1-NEXT: vmovq %xmm2, %rax
-; AVX1-NEXT: vmovq %xmm0, %rsi
-; AVX1-NEXT: addq %rax, %rsi
-; AVX1-NEXT: addq $-1, %rdi
-; AVX1-NEXT: movq %rdi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX1-NEXT: movl $0, %eax
-; AVX1-NEXT: adcq $-1, %rax
-; AVX1-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX1-NEXT: addq $-1, %rbp
-; AVX1-NEXT: movq %rbp, (%rsp) # 8-byte Spill
-; AVX1-NEXT: movl $0, %eax
-; AVX1-NEXT: adcq $-1, %rax
-; AVX1-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX1-NEXT: addq $-1, %r15
-; AVX1-NEXT: movq %r15, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX1-NEXT: movl $0, %eax
-; AVX1-NEXT: adcq $-1, %rax
-; AVX1-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX1-NEXT: addq $-1, %r10
-; AVX1-NEXT: movq %r10, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX1-NEXT: movl $0, %eax
-; AVX1-NEXT: adcq $-1, %rax
-; AVX1-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX1-NEXT: addq $-1, %rdx
-; AVX1-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX1-NEXT: movl $0, %eax
-; AVX1-NEXT: adcq $-1, %rax
-; AVX1-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX1-NEXT: addq $-1, %r8
-; AVX1-NEXT: movq %r8, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX1-NEXT: movl $0, %r12d
-; AVX1-NEXT: adcq $-1, %r12
-; AVX1-NEXT: addq $-1, %rcx
-; AVX1-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX1-NEXT: movl $0, %eax
-; AVX1-NEXT: adcq $-1, %rax
-; AVX1-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX1-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
-; AVX1-NEXT: addq $-1, %rax
-; AVX1-NEXT: movl $0, %ecx
-; AVX1-NEXT: adcq $-1, %rcx
-; AVX1-NEXT: addq $-1, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill
-; AVX1-NEXT: movl $0, %edx
-; AVX1-NEXT: adcq $-1, %rdx
-; AVX1-NEXT: addq $-1, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill
-; AVX1-NEXT: movl $0, %r15d
-; AVX1-NEXT: adcq $-1, %r15
-; AVX1-NEXT: addq $-1, %r13
-; AVX1-NEXT: movl $0, %r14d
-; AVX1-NEXT: adcq $-1, %r14
-; AVX1-NEXT: addq $-1, %rbx
-; AVX1-NEXT: movl $0, %r11d
-; AVX1-NEXT: adcq $-1, %r11
-; AVX1-NEXT: addq $-1, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill
-; AVX1-NEXT: movl $0, %r8d
-; AVX1-NEXT: adcq $-1, %r8
-; AVX1-NEXT: addq $-1, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill
-; AVX1-NEXT: movl $0, %edi
-; AVX1-NEXT: adcq $-1, %rdi
-; AVX1-NEXT: addq $-1, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill
-; AVX1-NEXT: movl $0, %r10d
-; AVX1-NEXT: adcq $-1, %r10
-; AVX1-NEXT: movq %rsi, %rbp
-; AVX1-NEXT: addq $-1, %rbp
-; AVX1-NEXT: movl $0, %r9d
-; AVX1-NEXT: adcq $-1, %r9
-; AVX1-NEXT: shldq $63, %rbx, %r11
-; AVX1-NEXT: shldq $63, %r13, %r14
-; AVX1-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rbx # 8-byte Reload
-; AVX1-NEXT: shldq $63, %rbx, %r15
-; AVX1-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rbx # 8-byte Reload
-; AVX1-NEXT: shldq $63, %rbx, %rdx
-; AVX1-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX1-NEXT: shldq $63, %rax, %rcx
-; AVX1-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX1-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
-; AVX1-NEXT: shldq $63, %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill
-; AVX1-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
-; AVX1-NEXT: shldq $63, %rax, %r12
-; AVX1-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rsi # 8-byte Reload
-; AVX1-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
-; AVX1-NEXT: shldq $63, %rax, %rsi
-; AVX1-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload
-; AVX1-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
-; AVX1-NEXT: shldq $63, %rax, %rdx
-; AVX1-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
-; AVX1-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
-; AVX1-NEXT: shldq $63, %rax, %rcx
+; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm4[4],xmm7[4],xmm4[5],xmm7[5],xmm4[6],xmm7[6],xmm4[7],xmm7[7]
+; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm5 = xmm1[2],xmm7[2],xmm1[3],xmm7[3]
+; AVX1-NEXT: vpextrq $1, %xmm5, %rbx
+; AVX1-NEXT: vmovq %xmm5, %rdx
+; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm5 = xmm3[4],xmm7[4],xmm3[5],xmm7[5],xmm3[6],xmm7[6],xmm3[7],xmm7[7]
+; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
+; AVX1-NEXT: vpextrq $1, %xmm1, %r9
+; AVX1-NEXT: vmovq %xmm1, %r10
+; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm1 = xmm4[0],zero,xmm4[1],zero,xmm4[2],zero,xmm4[3],zero
+; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm4 = xmm1[2],xmm7[2],xmm1[3],xmm7[3]
+; AVX1-NEXT: vmovd %xmm6, %esi
+; AVX1-NEXT: vpextrd $1, %xmm6, %edi
+; AVX1-NEXT: vpextrd $2, %xmm6, %eax
+; AVX1-NEXT: vpextrd $3, %xmm6, %ebp
+; AVX1-NEXT: vpextrd $3, %xmm5, %ecx
+; AVX1-NEXT: leal -1(%rbp,%rcx), %ecx
+; AVX1-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; AVX1-NEXT: vpextrd $2, %xmm5, %ecx
+; AVX1-NEXT: leal -1(%rax,%rcx), %eax
+; AVX1-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; AVX1-NEXT: vpextrd $1, %xmm5, %ecx
+; AVX1-NEXT: leal -1(%rdi,%rcx), %eax
+; AVX1-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; AVX1-NEXT: vmovd %xmm5, %ecx
+; AVX1-NEXT: leal -1(%rsi,%rcx), %r8d
+; AVX1-NEXT: vpextrq $1, %xmm4, %rcx
+; AVX1-NEXT: leal -1(%r15,%rbx), %r15d
+; AVX1-NEXT: vmovq %xmm4, %rsi
+; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm3 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero
+; AVX1-NEXT: leal -1(%r12,%rdx), %edx
+; AVX1-NEXT: vmovd %xmm2, %r12d
+; AVX1-NEXT: leal -1(%r11,%r9), %r11d
+; AVX1-NEXT: vpextrd $1, %xmm2, %edi
; AVX1-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
-; AVX1-NEXT: movq (%rsp), %rbx # 8-byte Reload
-; AVX1-NEXT: shldq $63, %rbx, %rax
-; AVX1-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rbx # 8-byte Reload
-; AVX1-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r13 # 8-byte Reload
-; AVX1-NEXT: shldq $63, %r13, %rbx
-; AVX1-NEXT: shldq $63, %rbp, %r9
-; AVX1-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rbp # 8-byte Reload
-; AVX1-NEXT: shldq $63, %rbp, %r10
-; AVX1-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rbp # 8-byte Reload
-; AVX1-NEXT: shldq $63, %rbp, %rdi
-; AVX1-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rbp # 8-byte Reload
-; AVX1-NEXT: shldq $63, %rbp, %r8
-; AVX1-NEXT: vmovq %rbx, %xmm8
-; AVX1-NEXT: vmovq %rax, %xmm0
-; AVX1-NEXT: vmovq %rcx, %xmm1
-; AVX1-NEXT: vmovq %rdx, %xmm11
-; AVX1-NEXT: vmovq %rsi, %xmm2
-; AVX1-NEXT: vmovq %r12, %xmm13
-; AVX1-NEXT: vmovq %r8, %xmm14
-; AVX1-NEXT: vmovq %rdi, %xmm15
-; AVX1-NEXT: vmovsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm9 # 8-byte Reload
-; AVX1-NEXT: # xmm9 = mem[0],zero
-; AVX1-NEXT: vmovsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm10 # 8-byte Reload
-; AVX1-NEXT: # xmm10 = mem[0],zero
-; AVX1-NEXT: vmovq {{[-0-9]+}}(%r{{[sb]}}p), %xmm12 # 8-byte Folded Reload
-; AVX1-NEXT: # xmm12 = mem[0],zero
-; AVX1-NEXT: vmovq %r15, %xmm3
-; AVX1-NEXT: vmovq %r14, %xmm4
-; AVX1-NEXT: vmovq %r11, %xmm5
-; AVX1-NEXT: vmovq %r10, %xmm6
-; AVX1-NEXT: vmovq %r9, %xmm7
-; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm8 = xmm0[0],xmm8[0]
-; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm11[0],xmm1[0]
-; AVX1-NEXT: vshufps {{.*#+}} xmm8 = xmm0[0,2],xmm8[0,2]
-; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm13[0],xmm2[0]
-; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm15[0],xmm14[0]
-; AVX1-NEXT: vshufps {{.*#+}} xmm11 = xmm1[0,2],xmm0[0,2]
-; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
-; AVX1-NEXT: vpshufb %xmm1, %xmm8, %xmm0
-; AVX1-NEXT: vpshufb %xmm1, %xmm11, %xmm2
-; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm2[0],xmm0[0]
-; AVX1-NEXT: vmovlhps {{.*#+}} xmm2 = xmm10[0],xmm9[0]
-; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm12[0]
-; AVX1-NEXT: vshufps {{.*#+}} xmm2 = xmm3[0,2],xmm2[0,2]
-; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm5[0],xmm4[0]
-; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [255,255,255,255,255,255,255,255]
-; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm0
-; AVX1-NEXT: vpshufb %xmm1, %xmm2, %xmm2
-; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm5 = xmm7[0],xmm6[0]
-; AVX1-NEXT: vshufps {{.*#+}} xmm3 = xmm5[0,2],xmm3[0,2]
-; AVX1-NEXT: vpshufb %xmm1, %xmm3, %xmm1
-; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
-; AVX1-NEXT: vpand %xmm4, %xmm1, %xmm1
-; AVX1-NEXT: vpackuswb %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: leal -1(%rax,%r10), %r10d
+; AVX1-NEXT: vpextrd $2, %xmm2, %ebx
+; AVX1-NEXT: leal -1(%r13,%rcx), %r9d
+; AVX1-NEXT: vpextrd $3, %xmm2, %ecx
+; AVX1-NEXT: leal -1(%r14,%rsi), %esi
+; AVX1-NEXT: vpextrd $3, %xmm3, %eax
+; AVX1-NEXT: leal -1(%rcx,%rax), %ecx
+; AVX1-NEXT: vpextrd $2, %xmm3, %eax
+; AVX1-NEXT: leal -1(%rbx,%rax), %ebx
+; AVX1-NEXT: vpextrd $1, %xmm3, %eax
+; AVX1-NEXT: leal -1(%rdi,%rax), %eax
+; AVX1-NEXT: vmovd %xmm3, %edi
+; AVX1-NEXT: leal -1(%r12,%rdi), %edi
+; AVX1-NEXT: vpextrq $1, %xmm0, %r12
+; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
+; AVX1-NEXT: vpextrq $1, %xmm1, %r13
+; AVX1-NEXT: leal -1(%r12,%r13), %r12d
+; AVX1-NEXT: vmovq %xmm0, %r13
+; AVX1-NEXT: vmovq %xmm1, %r14
+; AVX1-NEXT: leal -1(%r13,%r14), %ebp
+; AVX1-NEXT: shrl %ebp
+; AVX1-NEXT: vmovd %ebp, %xmm0
+; AVX1-NEXT: shrl %r12d
+; AVX1-NEXT: vpinsrb $1, %r12d, %xmm0, %xmm0
+; AVX1-NEXT: shrl %esi
+; AVX1-NEXT: vpinsrb $2, %esi, %xmm0, %xmm0
+; AVX1-NEXT: shrl %r9d
+; AVX1-NEXT: vpinsrb $3, %r9d, %xmm0, %xmm0
+; AVX1-NEXT: shrl %r10d
+; AVX1-NEXT: vpinsrb $4, %r10d, %xmm0, %xmm0
+; AVX1-NEXT: shrl %r11d
+; AVX1-NEXT: vpinsrb $5, %r11d, %xmm0, %xmm0
+; AVX1-NEXT: shrl %edx
+; AVX1-NEXT: vpinsrb $6, %edx, %xmm0, %xmm0
+; AVX1-NEXT: shrl %r15d
+; AVX1-NEXT: vpinsrb $7, %r15d, %xmm0, %xmm0
+; AVX1-NEXT: shrl %edi
+; AVX1-NEXT: vpinsrb $8, %edi, %xmm0, %xmm0
+; AVX1-NEXT: shrl %eax
+; AVX1-NEXT: vpinsrb $9, %eax, %xmm0, %xmm0
+; AVX1-NEXT: shrl %ebx
+; AVX1-NEXT: vpinsrb $10, %ebx, %xmm0, %xmm0
+; AVX1-NEXT: shrl %ecx
+; AVX1-NEXT: vpinsrb $11, %ecx, %xmm0, %xmm0
+; AVX1-NEXT: shrl %r8d
+; AVX1-NEXT: vpinsrb $12, %r8d, %xmm0, %xmm0
+; AVX1-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
+; AVX1-NEXT: shrl %eax
+; AVX1-NEXT: vpinsrb $13, %eax, %xmm0, %xmm0
+; AVX1-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
+; AVX1-NEXT: shrl %eax
+; AVX1-NEXT: vpinsrb $14, %eax, %xmm0, %xmm0
+; AVX1-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
+; AVX1-NEXT: shrl %eax
+; AVX1-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0
; AVX1-NEXT: vmovdqu %xmm0, (%rax)
-; AVX1-NEXT: addq $24, %rsp
; AVX1-NEXT: popq %rbx
; AVX1-NEXT: popq %r12
; AVX1-NEXT: popq %r13
@@ -2294,237 +2171,123 @@ define void @not_avg_v16i8_wide_constant
; AVX2-NEXT: pushq %r13
; AVX2-NEXT: pushq %r12
; AVX2-NEXT: pushq %rbx
-; AVX2-NEXT: subq $16, %rsp
; AVX2-NEXT: vpmovzxbw {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero,mem[8],zero,mem[9],zero,mem[10],zero,mem[11],zero,mem[12],zero,mem[13],zero,mem[14],zero,mem[15],zero
-; AVX2-NEXT: vpmovzxbw {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero,mem[8],zero,mem[9],zero,mem[10],zero,mem[11],zero,mem[12],zero,mem[13],zero,mem[14],zero,mem[15],zero
-; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm2
-; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero
-; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm3 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero
-; AVX2-NEXT: vextracti128 $1, %ymm3, %xmm4
-; AVX2-NEXT: vpextrq $1, %xmm4, %rbx
-; AVX2-NEXT: vmovq %xmm4, %rbp
-; AVX2-NEXT: vpextrq $1, %xmm3, %rdi
-; AVX2-NEXT: vmovq %xmm3, %rcx
-; AVX2-NEXT: vextracti128 $1, %ymm2, %xmm2
+; AVX2-NEXT: vpmovzxbw {{.*#+}} ymm3 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero,mem[8],zero,mem[9],zero,mem[10],zero,mem[11],zero,mem[12],zero,mem[13],zero,mem[14],zero,mem[15],zero
+; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm2 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
+; AVX2-NEXT: vextracti128 $1, %ymm2, %xmm0
+; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm4 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
+; AVX2-NEXT: vextracti128 $1, %ymm4, %xmm0
+; AVX2-NEXT: vpextrq $1, %xmm4, %r14
+; AVX2-NEXT: vmovq %xmm4, %r13
; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero
-; AVX2-NEXT: vextracti128 $1, %ymm2, %xmm3
-; AVX2-NEXT: vpextrq $1, %xmm3, %rdx
-; AVX2-NEXT: vmovq %xmm3, %r9
-; AVX2-NEXT: vpextrq $1, %xmm2, %r11
-; AVX2-NEXT: vmovq %xmm2, %r12
-; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
-; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm2 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
-; AVX2-NEXT: vextracti128 $1, %ymm2, %xmm3
-; AVX2-NEXT: vpextrq $1, %xmm3, %r15
-; AVX2-NEXT: vmovq %xmm3, %rsi
-; AVX2-NEXT: vpextrq $1, %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill
+; AVX2-NEXT: vextracti128 $1, %ymm2, %xmm4
+; AVX2-NEXT: vpextrq $1, %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill
+; AVX2-NEXT: vmovq %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill
; AVX2-NEXT: vmovq %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill
+; AVX2-NEXT: vpextrq $1, %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill
; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm1
-; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
+; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm2
-; AVX2-NEXT: vpextrq $1, %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill
-; AVX2-NEXT: vmovq %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill
-; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm2
-; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero
-; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm3 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero
-; AVX2-NEXT: vextracti128 $1, %ymm3, %xmm4
-; AVX2-NEXT: vpextrq $1, %xmm4, %rax
-; AVX2-NEXT: addq %rbx, %rax
-; AVX2-NEXT: movq %rax, %rbx
-; AVX2-NEXT: vmovq %xmm4, %r13
-; AVX2-NEXT: addq %rbp, %r13
-; AVX2-NEXT: vpextrq $1, %xmm3, %r10
-; AVX2-NEXT: addq %rdi, %r10
-; AVX2-NEXT: vmovq %xmm3, %r14
-; AVX2-NEXT: addq %rcx, %r14
-; AVX2-NEXT: vextracti128 $1, %ymm2, %xmm2
+; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm6 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero
+; AVX2-NEXT: vextracti128 $1, %ymm6, %xmm5
+; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm4 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
+; AVX2-NEXT: vextracti128 $1, %ymm4, %xmm7
+; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm2 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero,xmm3[4],zero,xmm3[5],zero,xmm3[6],zero,xmm3[7],zero
+; AVX2-NEXT: vextracti128 $1, %ymm2, %xmm1
+; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero
-; AVX2-NEXT: vextracti128 $1, %ymm2, %xmm3
-; AVX2-NEXT: vpextrq $1, %xmm3, %rax
-; AVX2-NEXT: addq %rdx, %rax
-; AVX2-NEXT: movq %rax, %rcx
-; AVX2-NEXT: vmovq %xmm3, %r8
-; AVX2-NEXT: addq %r9, %r8
-; AVX2-NEXT: vpextrq $1, %xmm2, %rax
-; AVX2-NEXT: addq %r11, %rax
-; AVX2-NEXT: movq %rax, %r11
-; AVX2-NEXT: vmovq %xmm2, %rax
-; AVX2-NEXT: addq %r12, %rax
-; AVX2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
-; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm2 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
-; AVX2-NEXT: vextracti128 $1, %ymm2, %xmm3
-; AVX2-NEXT: vpextrq $1, %xmm3, %rax
-; AVX2-NEXT: addq %r15, %rax
-; AVX2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX2-NEXT: vmovq %xmm3, %rax
-; AVX2-NEXT: addq %rsi, %rax
-; AVX2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX2-NEXT: vpextrq $1, %xmm2, %rax
-; AVX2-NEXT: addq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Folded Reload
-; AVX2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX2-NEXT: vmovq %xmm2, %rax
-; AVX2-NEXT: addq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Folded Reload
-; AVX2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
-; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
-; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm2
-; AVX2-NEXT: vpextrq $1, %xmm2, %rbp
-; AVX2-NEXT: addq {{[-0-9]+}}(%r{{[sb]}}p), %rbp # 8-byte Folded Reload
-; AVX2-NEXT: vmovq %xmm2, %r9
-; AVX2-NEXT: addq {{[-0-9]+}}(%r{{[sb]}}p), %r9 # 8-byte Folded Reload
-; AVX2-NEXT: vpextrq $1, %xmm1, %rax
-; AVX2-NEXT: vpextrq $1, %xmm0, %rdi
-; AVX2-NEXT: addq %rax, %rdi
-; AVX2-NEXT: vmovq %xmm1, %rdx
-; AVX2-NEXT: vmovq %xmm0, %rsi
-; AVX2-NEXT: addq %rdx, %rsi
-; AVX2-NEXT: addq $-1, %rbx
-; AVX2-NEXT: movq %rbx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX2-NEXT: movl $0, %eax
-; AVX2-NEXT: adcq $-1, %rax
-; AVX2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX2-NEXT: addq $-1, %r13
-; AVX2-NEXT: movq %r13, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX2-NEXT: movl $0, %eax
-; AVX2-NEXT: adcq $-1, %rax
-; AVX2-NEXT: movq %rax, (%rsp) # 8-byte Spill
-; AVX2-NEXT: addq $-1, %r10
-; AVX2-NEXT: movq %r10, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX2-NEXT: movl $0, %eax
-; AVX2-NEXT: adcq $-1, %rax
-; AVX2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX2-NEXT: addq $-1, %r14
-; AVX2-NEXT: movq %r14, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX2-NEXT: movl $0, %r13d
-; AVX2-NEXT: adcq $-1, %r13
-; AVX2-NEXT: addq $-1, %rcx
-; AVX2-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX2-NEXT: movl $0, %eax
-; AVX2-NEXT: adcq $-1, %rax
-; AVX2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX2-NEXT: addq $-1, %r8
-; AVX2-NEXT: movq %r8, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX2-NEXT: movl $0, %r15d
-; AVX2-NEXT: adcq $-1, %r15
-; AVX2-NEXT: addq $-1, %r11
-; AVX2-NEXT: movq %r11, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX2-NEXT: movl $0, %ebx
-; AVX2-NEXT: adcq $-1, %rbx
-; AVX2-NEXT: addq $-1, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill
-; AVX2-NEXT: movl $0, %r8d
-; AVX2-NEXT: adcq $-1, %r8
-; AVX2-NEXT: addq $-1, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill
-; AVX2-NEXT: movl $0, %eax
-; AVX2-NEXT: adcq $-1, %rax
-; AVX2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX2-NEXT: addq $-1, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill
-; AVX2-NEXT: movl $0, %eax
-; AVX2-NEXT: adcq $-1, %rax
-; AVX2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX2-NEXT: addq $-1, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill
-; AVX2-NEXT: movl $0, %r12d
-; AVX2-NEXT: adcq $-1, %r12
-; AVX2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
-; AVX2-NEXT: addq $-1, %rcx
-; AVX2-NEXT: movl $0, %r11d
-; AVX2-NEXT: adcq $-1, %r11
-; AVX2-NEXT: addq $-1, %rbp
-; AVX2-NEXT: movl $0, %r14d
-; AVX2-NEXT: adcq $-1, %r14
-; AVX2-NEXT: addq $-1, %r9
-; AVX2-NEXT: movl $0, %r10d
-; AVX2-NEXT: adcq $-1, %r10
-; AVX2-NEXT: addq $-1, %rdi
-; AVX2-NEXT: movl $0, %edx
-; AVX2-NEXT: adcq $-1, %rdx
-; AVX2-NEXT: addq $-1, %rsi
-; AVX2-NEXT: movl $0, %eax
-; AVX2-NEXT: adcq $-1, %rax
-; AVX2-NEXT: shldq $63, %rsi, %rax
-; AVX2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX2-NEXT: shldq $63, %rdi, %rdx
-; AVX2-NEXT: shldq $63, %r9, %r10
-; AVX2-NEXT: shldq $63, %rbp, %r14
-; AVX2-NEXT: shldq $63, %rcx, %r11
-; AVX2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
-; AVX2-NEXT: shldq $63, %rcx, %r12
-; AVX2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
-; AVX2-NEXT: shldq $63, %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill
-; AVX2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
-; AVX2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r9 # 8-byte Reload
-; AVX2-NEXT: shldq $63, %rcx, %r9
-; AVX2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
-; AVX2-NEXT: shldq $63, %rcx, %r8
+; AVX2-NEXT: vmovd %xmm4, %r12d
+; AVX2-NEXT: vpextrd $2, %xmm4, %r15d
+; AVX2-NEXT: vextracti128 $1, %ymm2, %xmm4
+; AVX2-NEXT: vextracti128 $1, %ymm3, %xmm3
+; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm3 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero,xmm3[4],zero,xmm3[5],zero,xmm3[6],zero,xmm3[7],zero
+; AVX2-NEXT: vmovd %xmm7, %ecx
+; AVX2-NEXT: vpextrd $2, %xmm7, %edi
+; AVX2-NEXT: vextracti128 $1, %ymm3, %xmm7
+; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm7 = xmm7[0],zero,xmm7[1],zero,xmm7[2],zero,xmm7[3],zero
+; AVX2-NEXT: vmovd %xmm6, %ebx
+; AVX2-NEXT: vpextrd $2, %xmm6, %esi
+; AVX2-NEXT: vextracti128 $1, %ymm7, %xmm6
+; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm3 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero
+; AVX2-NEXT: vmovd %xmm5, %edx
+; AVX2-NEXT: vpextrd $2, %xmm5, %ebp
+; AVX2-NEXT: vextracti128 $1, %ymm3, %xmm5
+; AVX2-NEXT: vpextrd $2, %xmm6, %eax
+; AVX2-NEXT: leal -1(%rbp,%rax), %eax
+; AVX2-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; AVX2-NEXT: vmovd %xmm6, %eax
+; AVX2-NEXT: leal -1(%rdx,%rax), %eax
+; AVX2-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; AVX2-NEXT: vpextrd $2, %xmm7, %eax
+; AVX2-NEXT: leal -1(%rsi,%rax), %r11d
+; AVX2-NEXT: vmovd %xmm7, %eax
+; AVX2-NEXT: leal -1(%rbx,%rax), %r10d
+; AVX2-NEXT: vpextrd $2, %xmm5, %eax
+; AVX2-NEXT: leal -1(%rdi,%rax), %r9d
+; AVX2-NEXT: vmovd %xmm5, %eax
+; AVX2-NEXT: leal -1(%rcx,%rax), %r8d
+; AVX2-NEXT: vpextrd $2, %xmm3, %eax
+; AVX2-NEXT: leal -1(%r15,%rax), %r15d
+; AVX2-NEXT: vmovd %xmm3, %ecx
+; AVX2-NEXT: leal -1(%r12,%rcx), %r12d
+; AVX2-NEXT: vpextrq $1, %xmm2, %rdx
; AVX2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
-; AVX2-NEXT: shldq $63, %rax, %rbx
+; AVX2-NEXT: leaq -1(%rax,%rdx), %rdx
+; AVX2-NEXT: vmovq %xmm2, %rsi
; AVX2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
-; AVX2-NEXT: shldq $63, %rax, %r15
+; AVX2-NEXT: leaq -1(%rax,%rsi), %rsi
+; AVX2-NEXT: vmovq %xmm4, %rbx
; AVX2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
-; AVX2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
-; AVX2-NEXT: shldq $63, %rcx, %rax
-; AVX2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
-; AVX2-NEXT: shldq $63, %rcx, %r13
-; AVX2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rbp # 8-byte Reload
-; AVX2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
-; AVX2-NEXT: shldq $63, %rcx, %rbp
-; AVX2-NEXT: movq (%rsp), %rdi # 8-byte Reload
-; AVX2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
-; AVX2-NEXT: shldq $63, %rcx, %rdi
-; AVX2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
-; AVX2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rsi # 8-byte Reload
-; AVX2-NEXT: shldq $63, %rcx, %rsi
-; AVX2-NEXT: vmovq %rsi, %xmm8
-; AVX2-NEXT: vmovq %rdi, %xmm9
-; AVX2-NEXT: vmovq %rbp, %xmm10
-; AVX2-NEXT: vmovq %r13, %xmm11
-; AVX2-NEXT: vmovq %rax, %xmm12
-; AVX2-NEXT: vmovq %r15, %xmm13
-; AVX2-NEXT: vmovq %rbx, %xmm14
-; AVX2-NEXT: vmovq %r8, %xmm15
-; AVX2-NEXT: vmovq %r9, %xmm0
-; AVX2-NEXT: vmovq {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Folded Reload
-; AVX2-NEXT: # xmm1 = mem[0],zero
-; AVX2-NEXT: vmovq %r12, %xmm2
-; AVX2-NEXT: vmovq %r11, %xmm3
-; AVX2-NEXT: vmovq %r14, %xmm4
-; AVX2-NEXT: vmovq %r10, %xmm5
-; AVX2-NEXT: vmovq %rdx, %xmm6
-; AVX2-NEXT: vmovq {{[-0-9]+}}(%r{{[sb]}}p), %xmm7 # 8-byte Folded Reload
-; AVX2-NEXT: # xmm7 = mem[0],zero
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm8 = xmm9[0],xmm8[0]
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm9 = xmm11[0],xmm10[0]
-; AVX2-NEXT: vinserti128 $1, %xmm8, %ymm9, %ymm8
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm9 = xmm13[0],xmm12[0]
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm15[0],xmm14[0]
-; AVX2-NEXT: vinserti128 $1, %xmm9, %ymm10, %ymm9
-; AVX2-NEXT: vpshufd {{.*#+}} ymm8 = ymm8[0,2,2,3,4,6,6,7]
-; AVX2-NEXT: vpermq {{.*#+}} ymm8 = ymm8[0,2,2,3]
-; AVX2-NEXT: vpshufd {{.*#+}} ymm9 = ymm9[0,2,2,3,4,6,6,7]
-; AVX2-NEXT: vpermq {{.*#+}} ymm9 = ymm9[0,2,2,3]
-; AVX2-NEXT: vinserti128 $1, %xmm9, %ymm8, %ymm8
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm3[0],xmm2[0]
-; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
-; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
-; AVX2-NEXT: vpshufb %ymm1, %ymm8, %ymm2
-; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3]
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm5[0],xmm4[0]
-; AVX2-NEXT: vmovdqa {{.*#+}} xmm4 = [255,255,255,255,255,255,255,255]
-; AVX2-NEXT: vpand %xmm4, %xmm2, %xmm2
-; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
-; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm5 = xmm7[0],xmm6[0]
-; AVX2-NEXT: vinserti128 $1, %xmm3, %ymm5, %ymm3
-; AVX2-NEXT: vpshufd {{.*#+}} ymm3 = ymm3[0,2,2,3,4,6,6,7]
-; AVX2-NEXT: vpermq {{.*#+}} ymm3 = ymm3[0,2,2,3]
-; AVX2-NEXT: vinserti128 $1, %xmm3, %ymm0, %ymm0
-; AVX2-NEXT: vpshufb %ymm1, %ymm0, %ymm0
-; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
-; AVX2-NEXT: vpand %xmm4, %xmm0, %xmm0
-; AVX2-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
+; AVX2-NEXT: leaq -1(%rax,%rbx), %rbx
+; AVX2-NEXT: vpextrq $1, %xmm4, %rbp
+; AVX2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; AVX2-NEXT: leaq -1(%rax,%rbp), %rbp
+; AVX2-NEXT: vmovq %xmm1, %rdi
+; AVX2-NEXT: leaq -1(%r13,%rdi), %rdi
+; AVX2-NEXT: vpextrq $1, %xmm1, %rax
+; AVX2-NEXT: leaq -1(%r14,%rax), %rax
+; AVX2-NEXT: vmovq %xmm0, %rcx
+; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm1
+; AVX2-NEXT: vmovq %xmm1, %r13
+; AVX2-NEXT: leaq -1(%rcx,%r13), %r13
+; AVX2-NEXT: vpextrq $1, %xmm0, %rcx
+; AVX2-NEXT: vpextrq $1, %xmm1, %r14
+; AVX2-NEXT: leaq -1(%rcx,%r14), %rcx
+; AVX2-NEXT: shrq %rsi
+; AVX2-NEXT: vmovd %esi, %xmm0
+; AVX2-NEXT: shrq %rdx
+; AVX2-NEXT: vpinsrb $1, %edx, %xmm0, %xmm0
+; AVX2-NEXT: shrq %rbx
+; AVX2-NEXT: vpinsrb $2, %ebx, %xmm0, %xmm0
+; AVX2-NEXT: shrq %rbp
+; AVX2-NEXT: vpinsrb $3, %ebp, %xmm0, %xmm0
+; AVX2-NEXT: shrq %rdi
+; AVX2-NEXT: vpinsrb $4, %edi, %xmm0, %xmm0
+; AVX2-NEXT: shrq %rax
+; AVX2-NEXT: vpinsrb $5, %eax, %xmm0, %xmm0
+; AVX2-NEXT: shrq %r13
+; AVX2-NEXT: vpinsrb $6, %r13d, %xmm0, %xmm0
+; AVX2-NEXT: shrq %rcx
+; AVX2-NEXT: vpinsrb $7, %ecx, %xmm0, %xmm0
+; AVX2-NEXT: shrl %r12d
+; AVX2-NEXT: vpinsrb $8, %r12d, %xmm0, %xmm0
+; AVX2-NEXT: shrl %r15d
+; AVX2-NEXT: vpinsrb $9, %r15d, %xmm0, %xmm0
+; AVX2-NEXT: shrl %r8d
+; AVX2-NEXT: vpinsrb $10, %r8d, %xmm0, %xmm0
+; AVX2-NEXT: shrl %r9d
+; AVX2-NEXT: vpinsrb $11, %r9d, %xmm0, %xmm0
+; AVX2-NEXT: shrl %r10d
+; AVX2-NEXT: vpinsrb $12, %r10d, %xmm0, %xmm0
+; AVX2-NEXT: shrl %r11d
+; AVX2-NEXT: vpinsrb $13, %r11d, %xmm0, %xmm0
+; AVX2-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
+; AVX2-NEXT: shrl %eax
+; AVX2-NEXT: vpinsrb $14, %eax, %xmm0, %xmm0
+; AVX2-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
+; AVX2-NEXT: shrl %eax
+; AVX2-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0
; AVX2-NEXT: vmovdqu %xmm0, (%rax)
-; AVX2-NEXT: addq $16, %rsp
; AVX2-NEXT: popq %rbx
; AVX2-NEXT: popq %r12
; AVX2-NEXT: popq %r13
@@ -2542,229 +2305,123 @@ define void @not_avg_v16i8_wide_constant
; AVX512-NEXT: pushq %r13
; AVX512-NEXT: pushq %r12
; AVX512-NEXT: pushq %rbx
-; AVX512-NEXT: subq $24, %rsp
-; AVX512-NEXT: vpmovzxbw {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero,mem[8],zero,mem[9],zero,mem[10],zero,mem[11],zero,mem[12],zero,mem[13],zero,mem[14],zero,mem[15],zero
; AVX512-NEXT: vpmovzxbw {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero,mem[8],zero,mem[9],zero,mem[10],zero,mem[11],zero,mem[12],zero,mem[13],zero,mem[14],zero,mem[15],zero
-; AVX512-NEXT: vpmovzxwd {{.*#+}} ymm2 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
-; AVX512-NEXT: vextracti128 $1, %ymm2, %xmm3
-; AVX512-NEXT: vpmovzxdq {{.*#+}} ymm3 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero
-; AVX512-NEXT: vextracti128 $1, %ymm3, %xmm4
-; AVX512-NEXT: vpextrq $1, %xmm4, %rbx
-; AVX512-NEXT: vmovq %xmm4, %rbp
-; AVX512-NEXT: vpextrq $1, %xmm3, %rdi
-; AVX512-NEXT: vmovq %xmm3, %rsi
-; AVX512-NEXT: vpmovzxdq {{.*#+}} ymm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero
-; AVX512-NEXT: vextracti128 $1, %ymm2, %xmm3
-; AVX512-NEXT: vpextrq $1, %xmm3, %rdx
-; AVX512-NEXT: vmovq %xmm3, %r8
-; AVX512-NEXT: vpextrq $1, %xmm2, %r13
-; AVX512-NEXT: vmovq %xmm2, %r12
-; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm0
-; AVX512-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
-; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm2
+; AVX512-NEXT: vpmovzxbw {{.*#+}} ymm3 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero,mem[8],zero,mem[9],zero,mem[10],zero,mem[11],zero,mem[12],zero,mem[13],zero,mem[14],zero,mem[15],zero
+; AVX512-NEXT: vpmovzxwd {{.*#+}} ymm2 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
+; AVX512-NEXT: vextracti128 $1, %ymm2, %xmm0
+; AVX512-NEXT: vpmovzxdq {{.*#+}} ymm4 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
+; AVX512-NEXT: vextracti128 $1, %ymm4, %xmm0
+; AVX512-NEXT: vpextrq $1, %xmm4, %r14
+; AVX512-NEXT: vmovq %xmm4, %r13
; AVX512-NEXT: vpmovzxdq {{.*#+}} ymm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero
-; AVX512-NEXT: vextracti128 $1, %ymm2, %xmm3
-; AVX512-NEXT: vpextrq $1, %xmm3, %r15
-; AVX512-NEXT: vmovq %xmm3, %r14
-; AVX512-NEXT: vpextrq $1, %xmm2, %r9
+; AVX512-NEXT: vextracti128 $1, %ymm2, %xmm4
+; AVX512-NEXT: vpextrq $1, %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill
+; AVX512-NEXT: vmovq %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill
; AVX512-NEXT: vmovq %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill
-; AVX512-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
-; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm2
; AVX512-NEXT: vpextrq $1, %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill
-; AVX512-NEXT: vmovq %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill
-; AVX512-NEXT: vpmovzxwd {{.*#+}} ymm2 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
-; AVX512-NEXT: vextracti128 $1, %ymm2, %xmm3
-; AVX512-NEXT: vpmovzxdq {{.*#+}} ymm3 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero
-; AVX512-NEXT: vextracti128 $1, %ymm3, %xmm4
-; AVX512-NEXT: vpextrq $1, %xmm4, %rax
-; AVX512-NEXT: addq %rbx, %rax
-; AVX512-NEXT: movq %rax, %rbx
-; AVX512-NEXT: vmovq %xmm4, %rax
-; AVX512-NEXT: addq %rbp, %rax
-; AVX512-NEXT: movq %rax, %rbp
-; AVX512-NEXT: vpextrq $1, %xmm3, %rax
-; AVX512-NEXT: addq %rdi, %rax
-; AVX512-NEXT: movq %rax, %rdi
-; AVX512-NEXT: vmovq %xmm3, %r10
-; AVX512-NEXT: addq %rsi, %r10
-; AVX512-NEXT: vpmovzxdq {{.*#+}} ymm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero
-; AVX512-NEXT: vextracti128 $1, %ymm2, %xmm3
-; AVX512-NEXT: vpextrq $1, %xmm3, %rcx
-; AVX512-NEXT: addq %rdx, %rcx
-; AVX512-NEXT: vmovq %xmm3, %rax
-; AVX512-NEXT: addq %r8, %rax
-; AVX512-NEXT: movq %rax, %r8
-; AVX512-NEXT: vpextrq $1, %xmm2, %rsi
-; AVX512-NEXT: addq %r13, %rsi
-; AVX512-NEXT: vmovq %xmm2, %r11
-; AVX512-NEXT: addq %r12, %r11
; AVX512-NEXT: vextracti128 $1, %ymm1, %xmm1
; AVX512-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
; AVX512-NEXT: vextracti128 $1, %ymm1, %xmm2
-; AVX512-NEXT: vpmovzxdq {{.*#+}} ymm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero
-; AVX512-NEXT: vextracti128 $1, %ymm2, %xmm3
-; AVX512-NEXT: vpextrq $1, %xmm3, %rax
-; AVX512-NEXT: addq %r15, %rax
-; AVX512-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX512-NEXT: vmovq %xmm3, %rax
-; AVX512-NEXT: addq %r14, %rax
-; AVX512-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX512-NEXT: vpextrq $1, %xmm2, %rax
-; AVX512-NEXT: addq %r9, %rax
-; AVX512-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX512-NEXT: vmovq %xmm2, %rax
-; AVX512-NEXT: addq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Folded Reload
-; AVX512-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; AVX512-NEXT: vpmovzxdq {{.*#+}} ymm6 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero
+; AVX512-NEXT: vextracti128 $1, %ymm6, %xmm5
+; AVX512-NEXT: vpmovzxdq {{.*#+}} ymm4 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
+; AVX512-NEXT: vextracti128 $1, %ymm4, %xmm7
+; AVX512-NEXT: vpmovzxwd {{.*#+}} ymm2 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero,xmm3[4],zero,xmm3[5],zero,xmm3[6],zero,xmm3[7],zero
+; AVX512-NEXT: vextracti128 $1, %ymm2, %xmm1
; AVX512-NEXT: vpmovzxdq {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
-; AVX512-NEXT: vextracti128 $1, %ymm1, %xmm2
-; AVX512-NEXT: vpextrq $1, %xmm2, %rax
-; AVX512-NEXT: addq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Folded Reload
-; AVX512-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX512-NEXT: vmovq %xmm2, %r14
-; AVX512-NEXT: addq {{[-0-9]+}}(%r{{[sb]}}p), %r14 # 8-byte Folded Reload
-; AVX512-NEXT: vpextrq $1, %xmm0, %rax
-; AVX512-NEXT: vpextrq $1, %xmm1, %r9
-; AVX512-NEXT: addq %rax, %r9
-; AVX512-NEXT: vmovq %xmm0, %rax
-; AVX512-NEXT: vmovq %xmm1, %rdx
-; AVX512-NEXT: addq %rax, %rdx
-; AVX512-NEXT: addq $-1, %rbx
-; AVX512-NEXT: movq %rbx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX512-NEXT: movl $0, %eax
-; AVX512-NEXT: adcq $-1, %rax
-; AVX512-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX512-NEXT: addq $-1, %rbp
-; AVX512-NEXT: movq %rbp, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX512-NEXT: movl $0, %eax
-; AVX512-NEXT: adcq $-1, %rax
-; AVX512-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX512-NEXT: addq $-1, %rdi
-; AVX512-NEXT: movq %rdi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX512-NEXT: movl $0, %eax
-; AVX512-NEXT: adcq $-1, %rax
-; AVX512-NEXT: movq %rax, (%rsp) # 8-byte Spill
-; AVX512-NEXT: addq $-1, %r10
-; AVX512-NEXT: movq %r10, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX512-NEXT: movl $0, %eax
-; AVX512-NEXT: adcq $-1, %rax
-; AVX512-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX512-NEXT: addq $-1, %rcx
-; AVX512-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX512-NEXT: movl $0, %eax
-; AVX512-NEXT: adcq $-1, %rax
-; AVX512-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX512-NEXT: addq $-1, %r8
-; AVX512-NEXT: movq %r8, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX512-NEXT: movl $0, %eax
-; AVX512-NEXT: adcq $-1, %rax
-; AVX512-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX512-NEXT: addq $-1, %rsi
-; AVX512-NEXT: movq %rsi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX512-NEXT: movl $0, %r13d
-; AVX512-NEXT: adcq $-1, %r13
-; AVX512-NEXT: addq $-1, %r11
-; AVX512-NEXT: movq %r11, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX512-NEXT: movl $0, %r15d
-; AVX512-NEXT: adcq $-1, %r15
-; AVX512-NEXT: addq $-1, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill
-; AVX512-NEXT: movl $0, %eax
-; AVX512-NEXT: adcq $-1, %rax
-; AVX512-NEXT: movq %rax, %rsi
-; AVX512-NEXT: addq $-1, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill
-; AVX512-NEXT: movl $0, %r12d
-; AVX512-NEXT: adcq $-1, %r12
-; AVX512-NEXT: addq $-1, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill
-; AVX512-NEXT: movl $0, %ebx
-; AVX512-NEXT: adcq $-1, %rbx
-; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rbp # 8-byte Reload
-; AVX512-NEXT: addq $-1, %rbp
-; AVX512-NEXT: movl $0, %r11d
-; AVX512-NEXT: adcq $-1, %r11
-; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
-; AVX512-NEXT: addq $-1, %rax
-; AVX512-NEXT: movl $0, %r10d
-; AVX512-NEXT: adcq $-1, %r10
-; AVX512-NEXT: addq $-1, %r14
-; AVX512-NEXT: movl $0, %r8d
-; AVX512-NEXT: adcq $-1, %r8
-; AVX512-NEXT: addq $-1, %r9
-; AVX512-NEXT: movl $0, %edi
-; AVX512-NEXT: adcq $-1, %rdi
-; AVX512-NEXT: addq $-1, %rdx
-; AVX512-NEXT: movl $0, %ecx
-; AVX512-NEXT: adcq $-1, %rcx
-; AVX512-NEXT: shldq $63, %rdx, %rcx
-; AVX512-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX512-NEXT: shldq $63, %r9, %rdi
-; AVX512-NEXT: shldq $63, %r14, %r8
-; AVX512-NEXT: shldq $63, %rax, %r10
-; AVX512-NEXT: shldq $63, %rbp, %r11
-; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload
-; AVX512-NEXT: shldq $63, %rdx, %rbx
-; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload
-; AVX512-NEXT: shldq $63, %rdx, %r12
-; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload
-; AVX512-NEXT: shldq $63, %rdx, %rsi
-; AVX512-NEXT: movq %rsi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
-; AVX512-NEXT: shldq $63, %rax, %r15
+; AVX512-NEXT: vpmovzxdq {{.*#+}} ymm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero
+; AVX512-NEXT: vmovd %xmm4, %r12d
+; AVX512-NEXT: vpextrd $2, %xmm4, %r15d
+; AVX512-NEXT: vextracti128 $1, %ymm2, %xmm4
+; AVX512-NEXT: vextracti128 $1, %ymm3, %xmm3
+; AVX512-NEXT: vpmovzxwd {{.*#+}} ymm3 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero,xmm3[4],zero,xmm3[5],zero,xmm3[6],zero,xmm3[7],zero
+; AVX512-NEXT: vmovd %xmm7, %ecx
+; AVX512-NEXT: vpextrd $2, %xmm7, %edi
+; AVX512-NEXT: vextracti128 $1, %ymm3, %xmm7
+; AVX512-NEXT: vpmovzxdq {{.*#+}} ymm7 = xmm7[0],zero,xmm7[1],zero,xmm7[2],zero,xmm7[3],zero
+; AVX512-NEXT: vmovd %xmm6, %ebx
+; AVX512-NEXT: vpextrd $2, %xmm6, %esi
+; AVX512-NEXT: vextracti128 $1, %ymm7, %xmm6
+; AVX512-NEXT: vpmovzxdq {{.*#+}} ymm3 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero
+; AVX512-NEXT: vmovd %xmm5, %edx
+; AVX512-NEXT: vpextrd $2, %xmm5, %ebp
+; AVX512-NEXT: vextracti128 $1, %ymm3, %xmm5
+; AVX512-NEXT: vpextrd $2, %xmm6, %eax
+; AVX512-NEXT: leal -1(%rbp,%rax), %eax
+; AVX512-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; AVX512-NEXT: vmovd %xmm6, %eax
+; AVX512-NEXT: leal -1(%rdx,%rax), %eax
+; AVX512-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; AVX512-NEXT: vpextrd $2, %xmm7, %eax
+; AVX512-NEXT: leal -1(%rsi,%rax), %r11d
+; AVX512-NEXT: vmovd %xmm7, %eax
+; AVX512-NEXT: leal -1(%rbx,%rax), %r10d
+; AVX512-NEXT: vpextrd $2, %xmm5, %eax
+; AVX512-NEXT: leal -1(%rdi,%rax), %r9d
+; AVX512-NEXT: vmovd %xmm5, %eax
+; AVX512-NEXT: leal -1(%rcx,%rax), %r8d
+; AVX512-NEXT: vpextrd $2, %xmm3, %eax
+; AVX512-NEXT: leal -1(%r15,%rax), %r15d
+; AVX512-NEXT: vmovd %xmm3, %ecx
+; AVX512-NEXT: leal -1(%r12,%rcx), %r12d
+; AVX512-NEXT: vpextrq $1, %xmm2, %rdx
; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
-; AVX512-NEXT: shldq $63, %rax, %r13
-; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rsi # 8-byte Reload
+; AVX512-NEXT: leaq -1(%rax,%rdx), %rdx
+; AVX512-NEXT: vmovq %xmm2, %rsi
; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
-; AVX512-NEXT: shldq $63, %rax, %rsi
-; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
+; AVX512-NEXT: leaq -1(%rax,%rsi), %rsi
+; AVX512-NEXT: vmovq %xmm4, %rbx
; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
-; AVX512-NEXT: shldq $63, %rax, %rcx
+; AVX512-NEXT: leaq -1(%rax,%rbx), %rbx
+; AVX512-NEXT: vpextrq $1, %xmm4, %rbp
; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
-; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload
-; AVX512-NEXT: shldq $63, %rdx, %rax
-; AVX512-NEXT: movq (%rsp), %r14 # 8-byte Reload
-; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload
-; AVX512-NEXT: shldq $63, %rdx, %r14
-; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r9 # 8-byte Reload
-; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload
-; AVX512-NEXT: shldq $63, %rdx, %r9
-; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload
-; AVX512-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rbp # 8-byte Reload
-; AVX512-NEXT: shldq $63, %rdx, %rbp
-; AVX512-NEXT: vmovq %rbp, %xmm8
-; AVX512-NEXT: vmovq %r9, %xmm9
-; AVX512-NEXT: vmovq %r14, %xmm10
-; AVX512-NEXT: vmovq %rax, %xmm11
-; AVX512-NEXT: vmovq %rcx, %xmm12
-; AVX512-NEXT: vmovq %rsi, %xmm13
-; AVX512-NEXT: vmovq %r13, %xmm14
-; AVX512-NEXT: vmovq %r15, %xmm15
-; AVX512-NEXT: vmovq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Folded Reload
-; AVX512-NEXT: # xmm0 = mem[0],zero
-; AVX512-NEXT: vmovq %r12, %xmm1
-; AVX512-NEXT: vmovq %rbx, %xmm2
-; AVX512-NEXT: vmovq %r11, %xmm3
-; AVX512-NEXT: vmovq %r10, %xmm4
-; AVX512-NEXT: vmovq %r8, %xmm5
-; AVX512-NEXT: vmovq %rdi, %xmm6
-; AVX512-NEXT: vmovq {{[-0-9]+}}(%r{{[sb]}}p), %xmm7 # 8-byte Folded Reload
-; AVX512-NEXT: # xmm7 = mem[0],zero
-; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm8 = xmm9[0],xmm8[0]
-; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm9 = xmm11[0],xmm10[0]
-; AVX512-NEXT: vinserti128 $1, %xmm8, %ymm9, %ymm8
-; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm9 = xmm13[0],xmm12[0]
-; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm10 = xmm15[0],xmm14[0]
-; AVX512-NEXT: vinserti128 $1, %xmm9, %ymm10, %ymm9
-; AVX512-NEXT: vinserti64x4 $1, %ymm8, %zmm9, %zmm8
-; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
-; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm3[0],xmm2[0]
-; AVX512-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
-; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm5[0],xmm4[0]
-; AVX512-NEXT: vpmovqd %zmm8, %ymm2
-; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm7[0],xmm6[0]
-; AVX512-NEXT: vinserti128 $1, %xmm1, %ymm3, %ymm1
-; AVX512-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
-; AVX512-NEXT: vpmovqd %zmm0, %ymm0
-; AVX512-NEXT: vinserti64x4 $1, %ymm0, %zmm2, %zmm0
-; AVX512-NEXT: vpmovdb %zmm0, (%rax)
-; AVX512-NEXT: addq $24, %rsp
+; AVX512-NEXT: leaq -1(%rax,%rbp), %rbp
+; AVX512-NEXT: vmovq %xmm1, %rdi
+; AVX512-NEXT: leaq -1(%r13,%rdi), %rdi
+; AVX512-NEXT: vpextrq $1, %xmm1, %rax
+; AVX512-NEXT: leaq -1(%r14,%rax), %rax
+; AVX512-NEXT: vmovq %xmm0, %rcx
+; AVX512-NEXT: vextracti128 $1, %ymm1, %xmm1
+; AVX512-NEXT: vmovq %xmm1, %r13
+; AVX512-NEXT: leaq -1(%rcx,%r13), %r13
+; AVX512-NEXT: vpextrq $1, %xmm0, %rcx
+; AVX512-NEXT: vpextrq $1, %xmm1, %r14
+; AVX512-NEXT: leaq -1(%rcx,%r14), %rcx
+; AVX512-NEXT: shrq %rsi
+; AVX512-NEXT: vmovd %esi, %xmm0
+; AVX512-NEXT: shrq %rdx
+; AVX512-NEXT: vpinsrb $1, %edx, %xmm0, %xmm0
+; AVX512-NEXT: shrq %rbx
+; AVX512-NEXT: vpinsrb $2, %ebx, %xmm0, %xmm0
+; AVX512-NEXT: shrq %rbp
+; AVX512-NEXT: vpinsrb $3, %ebp, %xmm0, %xmm0
+; AVX512-NEXT: shrq %rdi
+; AVX512-NEXT: vpinsrb $4, %edi, %xmm0, %xmm0
+; AVX512-NEXT: shrq %rax
+; AVX512-NEXT: vpinsrb $5, %eax, %xmm0, %xmm0
+; AVX512-NEXT: shrq %r13
+; AVX512-NEXT: vpinsrb $6, %r13d, %xmm0, %xmm0
+; AVX512-NEXT: shrq %rcx
+; AVX512-NEXT: vpinsrb $7, %ecx, %xmm0, %xmm0
+; AVX512-NEXT: shrl %r12d
+; AVX512-NEXT: vpinsrb $8, %r12d, %xmm0, %xmm0
+; AVX512-NEXT: shrl %r15d
+; AVX512-NEXT: vpinsrb $9, %r15d, %xmm0, %xmm0
+; AVX512-NEXT: shrl %r8d
+; AVX512-NEXT: vpinsrb $10, %r8d, %xmm0, %xmm0
+; AVX512-NEXT: shrl %r9d
+; AVX512-NEXT: vpinsrb $11, %r9d, %xmm0, %xmm0
+; AVX512-NEXT: shrl %r10d
+; AVX512-NEXT: vpinsrb $12, %r10d, %xmm0, %xmm0
+; AVX512-NEXT: shrl %r11d
+; AVX512-NEXT: vpinsrb $13, %r11d, %xmm0, %xmm0
+; AVX512-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
+; AVX512-NEXT: shrl %eax
+; AVX512-NEXT: vpinsrb $14, %eax, %xmm0, %xmm0
+; AVX512-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
+; AVX512-NEXT: shrl %eax
+; AVX512-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0
+; AVX512-NEXT: vmovdqu %xmm0, (%rax)
; AVX512-NEXT: popq %rbx
; AVX512-NEXT: popq %r12
; AVX512-NEXT: popq %r13
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