[PATCH] D54791: [AArch64] Fix disassembly of SXTL and UXTL aliases

Oliver Stannard via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Nov 21 05:32:10 PST 2018


olista01 created this revision.
olista01 added reviewers: rengolin, spatel.
Herald added subscribers: kristof.beyls, javed.absar.

These instructions are aliases of SSHLL and USHLL, and should be
preferred for disassembly.

We did already have aliases for these in the tablegen, but they were
not being used. The problem was that we actually had two aliases for
each, one each for the "generic" and "apple-neon" syntaxes. This made
the disassembly ambiguous, so tablegen was not emitting either of them.
The fix was to use one alias with both syntaxes in the string, so that
the correct one can be picked by the disassembler.

This fixes https://bugs.llvm.org/show_bug.cgi?id=39721


Repository:
  rL LLVM

https://reviews.llvm.org/D54791

Files:
  lib/Target/AArch64/AArch64InstrInfo.td
  test/CodeGen/AArch64/arm64-extend-int-to-fp.ll
  test/CodeGen/AArch64/arm64-fast-isel-noconvert.ll
  test/CodeGen/AArch64/arm64-ld1.ll
  test/CodeGen/AArch64/arm64-scvt.ll
  test/CodeGen/AArch64/arm64-subvector-extend.ll
  test/CodeGen/AArch64/arm64-vbitwise.ll
  test/CodeGen/AArch64/arm64-vector-ext.ll
  test/CodeGen/AArch64/complex-int-to-fp.ll
  test/CodeGen/AArch64/fast-isel-cmp-vec.ll
  test/CodeGen/AArch64/fdiv_combine.ll
  test/CodeGen/AArch64/fp16-v4-instructions.ll
  test/CodeGen/AArch64/fp16-v8-instructions.ll
  test/CodeGen/AArch64/neon-shift-left-long.ll
  test/CodeGen/AArch64/sitofp-fixed-legal.ll
  test/MC/AArch64/arm64-aliases.s
  test/MC/AArch64/neon-sxtl.s
  test/MC/AArch64/neon-uxtl.s

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