[PATCH] D54783: [Power9] suboptimal vec_abs for some cases

[Kewen Lin via Phabricator via llvm-commits]

jedilyn created this revision.
jedilyn added reviewers: jsji, nemanjai, hfinkel, echristo, inouehrs.
Herald added a subscriber: hiraditya.

The current code sequence & its cycles for vec_abs look like:

  signed char:           tot cycs: 3+2+3 = 8
      xxspltib 35, 128  
      vaddubm 2, 2, 3  
      vabsdub 2, 2, 3  
  
  signed short:          tot cycs: 2+2+3+2+3 = 12
      lis 3, -32768      
      ori 3, 3, 32768    
      mtvsrws 35, 3      
      vadduhm 2, 2, 3  
      vabsduh 2, 2, 3  
  
  signed word:           tot cycs: 2 (parallel 2) + 2 + 3 = 7
      vxor 3, 3, 3       
      xvnegsp 34, 34
      xvnegsp 35, 35
      vabsduw 2, 2, 3

It can be better like:

  signed char:           tot cycs: 2 + 2 + 3 = 7
      xxlxor 35, 35, 35 
      vsububm 3, 3, 2
      vmaxsb 2, 2, 3
  
  signed short:          tot cycs: 2 + 2 + 3 = 7
      xxlxor 35, 35, 35
      vsubuhm 3, 3, 2
      vmaxsh 2, 2, 3
  
  signed word:           tot cycs: 2 + 3 = 5
      vnegw 0,2
      vmaxsw 2,0,2

The current implementation is intended to use absolute different instructions introduced in Power9, but it's for unsigned integers and we won't see any benefits with more efforts to support it for signed.


Repository:
  rL LLVM

https://reviews.llvm.org/D54783

Files:
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll
  llvm/test/CodeGen/PowerPC/pre-inc-disable.ll

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