[PATCH] D54663: [PowerPC] Complete the custom legalization of vector int to fp conversion

[Roland Froese via Phabricator via llvm-commits]

RolandF added a comment.

Nice!  Glad to see this stuff get completed.



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Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:7333
+    Arrange = DAG.getBitcast(IntermediateVT, Arrange);
+    Extend = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, IntermediateVT, Arrange,
+                         DAG.getValueType(Op.getOperand(0).getValueType()));
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When I looked at this before, I found that using SIGN_EXTEND_INREG led to a perm/shift left/shift right pattern, and I thought that using unpack would be faster for the signed int/pwr8 case.


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Comment at: test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll:340
+; CHECK-P8-NEXT:    vmrglh v2, v2, v2
+; CHECK-P8-NEXT:    vslw v2, v2, v3
+; CHECK-P8-NEXT:    vsraw v2, v2, v3
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I think using unpack would be faster than perm/vslw/vsraw, particularly for the f32 case where one level of unpack would do.


Repository:
  rL LLVM

https://reviews.llvm.org/D54663