[PATCH] D54143: [WIP, RISCV] Generate address sequences suitable for mcmodel=medium

[James Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

In https://reviews.llvm.org/D54143#1289972, @lewis-revill wrote:

> Deduplicate switch statements and error on an unsupported code model. Added a wrapper for loading the PC-relative address, which is expanded in `RISCVExpandPseudoInsts`. This approach is a compromise between splitting up into `auipc` and `addi` too early and blocking optimisations due to an additional basic block and splitting up too late and losing the chance to optimize the black box pseudo instruction.


Why do we need a new wrapper? Can't we re-use `PseudoLLA` (with `isAsmParserOnly` modified to 0 of course), as this is precisely an `lla`?


Repository:
  rL LLVM

https://reviews.llvm.org/D54143