[PATCH] D54358: [AMDGPU] Disable DAG combine at -O0
Stanislav Mekhanoshin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 19 11:58:52 PST 2018
rampitec marked an inline comment as done.
rampitec added inline comments.
================
Comment at: lib/Target/AMDGPU/SIISelLowering.cpp:8704-8721
case ISD::SCALAR_TO_VECTOR: {
SelectionDAG &DAG = DCI.DAG;
EVT VT = N->getValueType(0);
// v2i16 (scalar_to_vector i16:x) -> v2i16 (bitcast (any_extend i16:x))
if (VT == MVT::v2i16 || VT == MVT::v2f16) {
SDLoc SL(N);
----------------
scott.linder wrote:
> The only regression I see is for something of the form:
>
> ```
> target triple = "amdgcn-amd-amdhsa"
>
> ; Function Attrs: noinline optnone
> define void @spam() #0 {
> %tmp = load <3 x i16>, <3 x i16> addrspace(5)* undef, align 8
> %tmp1 = insertelement <3 x i16> %tmp, i16 0, i64 0
> store <3 x i16> %tmp1, <3 x i16> addrspace(5)* undef, align 8
> ret void
> }
>
> attributes #0 = { noinline optnone "target-cpu"="fiji" }
> ```
>
> For which we produce:
>
> ```
> Optimized legalized selection DAG: %bb.0 'spam:'
> SelectionDAG has 19 nodes:
> t0: ch = EntryToken
> t43: v2i16 = scalar_to_vector Constant:i16<0>
> t57: i32 = bitcast t43
> t68: ch = store<(store 2 into `<3 x i16> addrspace(5)* undef`, align 8, addrspace 5), trunc to i16> t40:1, t57, undef:i32, undef:i32
> t41: v2i32 = BUILD_VECTOR t40, t40
> t63: i64 = bitcast t41
> t36: i64 = srl t63, Constant:i32<32>
> t37: i16 = truncate t36
> t21: ch = store<(store 2 into `<3 x i16> addrspace(5)* undef` + 4, align 4, addrspace 5)> t40:1, t37, undef:i32, undef:i32
> t22: ch = TokenFactor t68, t21
> t9: i64,ch = CopyFromReg t0, Register:i64 %0
> t11: ch,glue = CopyToReg t22, Register:i64 $sgpr30_sgpr31, t9
> t40: i32,ch = load<(load 4 from `<3 x i16> addrspace(5)* undef`, align 8, addrspace 5)> t0, undef:i32, undef:i32
> t12: ch = RET_FLAG t11, Register:i64 $sgpr30_sgpr31, t11:1
> ```
>
> And then fail to select `t43: v2i16 = scalar_to_vector Constant:i16<0>`
The fix for it here: D54718.
https://reviews.llvm.org/D54358
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