[llvm] r347288 - [PowerPC] Don't combine to bswap store on 1-byte truncating store

[Nemanja Ivanovic via llvm-commits]

Author: nemanjai
Date: Mon Nov 19 20:42:31 2018
New Revision: 347288

URL: http://llvm.org/viewvc/llvm-project?rev=347288&view=rev
Log:
[PowerPC] Don't combine to bswap store on 1-byte truncating store

Turns out that there was no check for a store that truncates down
to a single byte when combining a (store (bswap...)) into a byte-swapping
store. This patch just adds that check.

Fixes https://bugs.llvm.org/show_bug.cgi?id=39478.

Added:
    llvm/trunk/test/CodeGen/PowerPC/pr39478.ll
Modified:
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=347288&r1=347287&r2=347288&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Mon Nov 19 20:42:31 2018
@@ -12604,9 +12604,10 @@ SDValue PPCTargetLowering::PerformDAGCom
         (Op1VT == MVT::i32 || Op1VT == MVT::i16 ||
          (Subtarget.hasLDBRX() && Subtarget.isPPC64() && Op1VT == MVT::i64))) {
 
-      // STBRX can only handle simple types.
+      // STBRX can only handle simple types and it makes no sense to store less
+      // two bytes in byte-reversed order.
       EVT mVT = cast<StoreSDNode>(N)->getMemoryVT();
-      if (mVT.isExtended())
+      if (mVT.isExtended() || mVT.getSizeInBits() < 16)
         break;
 
       SDValue BSwapOp = N->getOperand(1).getOperand(0);

Added: llvm/trunk/test/CodeGen/PowerPC/pr39478.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/pr39478.ll?rev=347288&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/pr39478.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/pr39478.ll Mon Nov 19 20:42:31 2018
@@ -0,0 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs < %s | \
+; RUN:   FileCheck %s
+; RUN: llc -mtriple=powerpc64-unknown-unknown -verify-machineinstrs < %s | \
+; RUN:   FileCheck %s
+
+define void @pr39478() {
+; CHECK-LABEL: pr39478:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lwz 3, 0(3)
+; CHECK-NEXT:    stb 3, 0(3)
+; CHECK-NEXT:    blr
+entry:
+  %tmp32 = load i64, i64* undef, align 8
+  %tmp33 = load i32, i32* undef, align 4
+  %tmp34 = and i32 %tmp33, -256
+  %tmp35 = lshr i64 %tmp32, 32
+  %tmp36 = shl nuw nsw i64 %tmp35, 24
+  %tmp37 = trunc i64 %tmp36 to i32
+  %tmp38 = call i32 @llvm.bswap.i32(i32 %tmp37)
+  %tmp39 = or i32 %tmp38, %tmp34
+  store i32 %tmp39, i32* undef, align 4
+  ret void
+}
+
+declare i32 @llvm.bswap.i32(i32)