[PATCH] D54725: [SelectionDAG] Compute known bits and num sign bits for live out vector registers. Use it to add AssertZExt/AssertSExt in the live in basic blocks

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

Does this patch do anything for PR11730?
https://bugs.llvm.org/show_bug.cgi?id=11730

If so, it would be good to add a test based on that.



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Comment at: lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:700
 
     // Ignore non-scalar or non-integer values.
     SDValue Src = N->getOperand(2);
----------------
Code comment isn't correct now.


https://reviews.llvm.org/D54725